URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [sw/] [run_regression.pl] - Diff between revs 126 and 132

Rev 126	Rev 132
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`#`	`#`
`# ############################################################################`	`# ############################################################################`
`#`	`#`
`# run_regression.pl`	`# run_regression.pl`
`#`	`#`
`# $Id: run_regression.pl,v 1.7 2004-07-04 12:05:55 arniml Exp $`	`# $Id: run_regression.pl,v 1.8 2004-09-12 00:30:53 arniml Exp $`
`#`	`#`
`# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)`	`# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)`
`#`	`#`
`# All rights reserved`	`# All rights reserved`
`#`	`#`
Line 52...	Line 52...

`##############################################################################`	`##############################################################################`
`# Commands to call the different VHDL simulators.`	`# Commands to call the different VHDL simulators.`
`#`	`#`
`# GHDL`	`# GHDL`
`my $ghdl_simulator = './tb_behav_c0';`	`my $ghdl_simulator = './tb_behav_c0 --assert-level=error';`
`my $ghdl_simulator_vcd = $ghdl_simulator.' --vcd=temp.vcd';`	`my $ghdl_simulator_vcd = $ghdl_simulator.' --vcd=temp.vcd';`
`#`	`#`
`# Choose simulator:`	`# Choose simulator:`
`my $vhdl_simulator = $ghdl_simulator;`	`my $vhdl_simulator = $ghdl_simulator;`
`my $vhdl_simulator_vcd = $ghdl_simulator_vcd;`	`my $vhdl_simulator_vcd = $ghdl_simulator_vcd;`