URL
https://opencores.org/ocsvn/t48/t48/trunk
[/] [t48/] [tags/] [rel_1_0/] [README] - Diff between revs 115 and 137
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 115 |
Rev 137 |
Line 1... |
Line 1... |
|
|
README for the T48 uController project
|
README for the T48 uController project
|
======================================
|
======================================
|
Version: $Date: 2004-05-31 16:28:26 $
|
Version: $Date: 2004-09-16 20:45:12 $
|
|
|
|
|
Introduction
|
Introduction
|
------------
|
------------
|
|
|
Line 144... |
Line 144... |
The testbench for the t8048 sample system.
|
The testbench for the t8048 sample system.
|
|
|
* tb_t8039_behav_c0
|
* tb_t8039_behav_c0
|
The testbench for the 8039 sample system.
|
The testbench for the 8039 sample system.
|
|
|
To delete all intermediate data, each Makefile has a 'clean' target:
|
Each Makefile has a 'clean' target to delete all intermediate data:
|
|
|
$ make -f Makefile. clean
|
$ make -f Makefile. clean
|
|
|
|
The basic simple sequence list can be found in COMPILE_LIST. This can be
|
|
useful to quickly set up the analyze stage of any compiler or
|
|
synthesizer. Especially when synthesizing the code, you want to skip the VHDL
|
|
configurations in *-c.vhd and everything below the bench/ directory.
|
|
|
Preparation of the ROM Files
|
Preparation of the ROM Files
|
----------------------------
|
----------------------------
|
|
|
All testbenches listed above need two files in hex-format. They contain the
|
All testbenches listed above need two files in hex-format. They contain the
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.