| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- Interface Timing Checker.
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-- Interface Timing Checker.
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--
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--
|
-- $Id: if_timing.vhd,v 1.1 2004-04-25 16:24:10 arniml Exp $
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-- $Id: if_timing.vhd,v 1.2 2004-04-25 20:40:58 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
|
-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 96... |
Line 96... |
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Check RD
|
-- Check RD
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--
|
--
|
rd_check: process (rd_n_i)
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rd_check: process (rd_n_i)
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begin
|
begin
|
if rd_n_i'event then
|
|
|
|
case rd_n_i is
|
case rd_n_i is
|
-- RD active
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-- RD active
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when '0' =>
|
when '0' =>
|
-- tLAFC1: ALE to Control RD
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-- tLAFC1: ALE to Control RD
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assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
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assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
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| Line 122... |
Line 120... |
|
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when others =>
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when others =>
|
null;
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null;
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end case;
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end case;
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|
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end if;
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|
|
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end process rd_check;
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end process rd_check;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
|
|
|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
-- Check WR
|
-- Check WR
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--
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--
|
wr_check: process (wr_n_i)
|
wr_check: process (wr_n_i)
|
begin
|
begin
|
if wr_n_i'event then
|
|
|
|
case wr_n_i is
|
case wr_n_i is
|
-- WR active
|
-- WR active
|
when '0' =>
|
when '0' =>
|
-- tLAFC1: ALE to Control WR
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-- tLAFC1: ALE to Control WR
|
assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
|
assert (now - last_ale_fall_s) > (t_CY / 5 - 75 ns)
|
| Line 170... |
Line 164... |
|
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when others =>
|
when others =>
|
null;
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null;
|
end case;
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end case;
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|
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end if;
|
|
|
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end process wr_check;
|
end process wr_check;
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--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Check BUS
|
-- Check BUS
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--
|
--
|
bus_check: process (db_bus_i)
|
bus_check: process (db_bus_i)
|
begin
|
begin
|
if db_bus_i'event then
|
|
|
|
-- RD access
|
-- RD access
|
-- tAD1 and tRD1 are not checked as they are constraints for the
|
-- tAD1 and tRD1 are not checked as they are constraints for the
|
-- external memory, not the t48!
|
-- external memory, not the t48!
|
|
|
-- WR access
|
-- WR access
|
| Line 197... |
Line 187... |
report "Timing violation of tDW on BUS vs. WR!"
|
report "Timing violation of tDW on BUS vs. WR!"
|
severity error;
|
severity error;
|
|
|
end if;
|
end if;
|
|
|
|
-- Address strobe
|
|
if ale_i = '0' then
|
|
-- tLA: Addr Hold from ALE
|
|
assert (now - last_ale_fall_s) > (t_CY / 15 - 40 ns)
|
|
report "Timing violation of tLA on BUS vs. ALE!"
|
|
severity error;
|
end if;
|
end if;
|
|
|
end process bus_check;
|
end process bus_check;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
-- Check ALE
|
|
--
|
|
ale_check: process (ale_i)
|
|
variable t_CA1 : time;
|
|
variable t_AL : time;
|
|
begin
|
|
case ale_i is
|
|
when '0' =>
|
|
t_AL := t_CY * 2/15 - 110 ns;
|
|
|
|
-- tAL: Addr Setup to ALE
|
|
assert (now - last_bus_change_s) > t_AL
|
|
report "Timing violation of tAL on BUS vs. ALE!"
|
|
severity error;
|
|
assert (now - last_p2_change_s) > t_AL
|
|
report "Timing violation of tAL on P2 vs. ALE!"
|
|
severity error;
|
|
|
|
when '1' =>
|
|
-- tCA1: Control to ALE (RD, WR, PROG)
|
|
t_CA1 := t_CY / 15 - 40 ns;
|
|
|
|
assert (now - last_rd_n_rise_s) > t_CA1
|
|
report "Timing violation of tCA1 on RD vs. ALE!"
|
|
severity error;
|
|
assert (now - last_wr_n_rise_s) > t_CA1
|
|
report "Timing violation of tCA1 on WR vs. ALE!"
|
|
severity error;
|
|
assert (now - last_prog_n_rise_s) > t_CA1
|
|
report "Timing violation of tCA1 on PROG vs. ALE!"
|
|
severity error;
|
|
|
|
-- tCA2: Control to ALE (PSEN)
|
|
assert (now - last_psen_n_rise_s) > (t_CY * 4/15 - 40 ns)
|
|
report "Timing violation of tCA2 on PSEN vs. ALE!"
|
|
severity error;
|
|
|
|
-- tPL: Port 2 I/O Setup to ALE
|
|
assert (now - last_p2_change_s) > (t_CY * 4/15 - 200 ns)
|
|
report "Timing violation of tPL on P2 vs. ALE!"
|
|
severity error;
|
|
|
|
when others =>
|
|
null;
|
|
|
|
end case;
|
|
|
|
end process ale_check;
|
|
--
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Check P2
|
|
--
|
|
p2_check: process (p2_i)
|
|
begin
|
|
case ale_i is
|
|
when '0' =>
|
|
-- tLA: Addr Hold from ALE
|
|
assert ((now - last_ale_fall_s) > (t_CY / 15 - 40 ns)) or
|
|
now = 0 ns
|
|
report "Timing violation of tLA on P2 vs. ALE!"
|
|
severity error;
|
|
|
|
if last_ale_fall_s < last_ale_rise_s then
|
|
-- tPV: Port Output from ALE
|
|
assert (now - last_ale_fall_s) < (t_CY * 3/10 + 100 ns)
|
|
report "Timing violation of tPV on P2 vs. ALE!"
|
|
severity error;
|
|
end if;
|
|
|
|
if prog_n_i = '1' then
|
|
-- tPD: Output Data Hold
|
|
assert ((now - last_prog_n_rise_s) > (t_CY / 10 - 50 ns)) or
|
|
now = 0 ns
|
|
report "Timing violation of tPD on P2 vs. PROG!"
|
|
severity error;
|
|
|
|
end if;
|
|
|
|
when '1' =>
|
|
-- tLP: Port 2 I/O to ALE
|
|
assert (now - last_ale_rise_s) > (t_CY / 30 - 30 ns)
|
|
report "Timing violation of tLP on P2 vs. ALE!"
|
|
severity error;
|
|
|
|
when others =>
|
|
null;
|
|
|
|
end case;
|
|
|
|
end process p2_check;
|
|
--
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Check PROG
|
|
--
|
|
prog_check: process (prog_n_i)
|
|
begin
|
|
case prog_n_i is
|
|
when '1' =>
|
|
-- tPP: PROG Pulse Width
|
|
assert (now - last_prog_n_fall_s) > (t_CY * 7/10 - 250 ns)
|
|
report "Timing violation of tPP!"
|
|
severity error;
|
|
|
|
-- tDP: Output Data Setup
|
|
assert (now - last_p2_change_s) > (t_CY * 2/5 - 150 ns)
|
|
report "Timing violation of tDP on P2 vs. PROG!"
|
|
severity error;
|
|
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
|
end process prog_check;
|
|
--
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
-- Monitor XTAL
|
-- Monitor XTAL
|
--
|
--
|
xtal_mon: process
|
xtal_mon: process
|
begin
|
begin
|
last_xtal_rise_s <= 0 ns;
|
last_xtal_rise_s <= 0 ns;
|
| Line 409... |
Line 529... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.1 2004/04/25 16:24:10 arniml
|
|
-- initial check-in
|
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
