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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The testbench for t8048.
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-- The testbench for t8048.
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--
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--
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-- $Id: tb_t8048.vhd,v 1.5 2006-06-21 01:04:05 arniml Exp $
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-- $Id: tb_t8048.vhd,v 1.6 2006-06-22 00:21:28 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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entity tb_t8048 is
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entity tb_t8048 is
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end tb_t8048;
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end tb_t8048;
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use work.t48_core_comp_pack.generic_ram_ena;
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use work.t48_core_comp_pack.generic_ram_ena;
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use work.t48_system_comp_pack.t8048;
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use work.t48_tb_pack.all;
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use work.t48_tb_pack.all;
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architecture behav of tb_t8048 is
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architecture behav of tb_t8048 is
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-- clock period, 11 MHz
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-- clock period, 11 MHz
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constant period_c : time := 90 ns;
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constant period_c : time := 90 ns;
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component t8048
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component lpm_rom
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generic (
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LPM_WIDTH : positive;
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LPM_TYPE : string := "LPM_ROM";
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LPM_WIDTHAD : positive;
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LPM_NUMWORDS : natural := 0;
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LPM_FILE : string;
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LPM_ADDRESS_CONTROL : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_HINT : string := "UNUSED"
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);
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port (
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port (
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xtal_i : in std_logic;
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address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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reset_n_i : in std_logic;
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inclock : in std_logic;
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t0_b : inout std_logic;
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outclock : in std_logic;
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int_n_i : in std_logic;
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memenab : in std_logic;
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ea_i : in std_logic;
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q : out std_logic_vector(LPM_WIDTH-1 downto 0)
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rd_n_o : out std_logic;
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psen_n_o : out std_logic;
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wr_n_o : out std_logic;
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ale_o : out std_logic;
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db_b : inout std_logic_vector( 7 downto 0);
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t1_i : in std_logic;
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p2_b : inout std_logic_vector( 7 downto 0);
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p1_b : inout std_logic_vector( 7 downto 0);
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prog_n_o : out std_logic
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);
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);
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end component;
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end component;
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signal xtal_s : std_logic;
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signal xtal_s : std_logic;
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signal res_n_s : std_logic;
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signal res_n_s : std_logic;
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signal int_n_s : std_logic;
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signal int_n_s : std_logic;
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signal ale_s : std_logic;
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signal ale_s : std_logic;
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signal psen_n_s : std_logic;
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signal psen_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal rom_addr_s : std_logic_vector(11 downto 0);
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signal rom_data_s : std_logic_vector( 7 downto 0);
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signal ram_data_to_s : std_logic_vector( 7 downto 0);
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signal ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ram_addr_s : std_logic_vector( 7 downto 0);
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signal ram_we_s : std_logic;
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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signal ext_ram_addr_s : std_logic_vector( 7 downto 0);
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signal ext_mem_addr_s : std_logic_vector(11 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_we_s : std_logic;
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signal ext_ram_we_s : std_logic;
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signal ext_rom_data_s : std_logic_vector( 7 downto 0);
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signal rd_n_s : std_logic;
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signal rd_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal zero_s : std_logic;
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signal zero_s : std_logic;
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signal one_s : std_logic;
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signal one_s : std_logic;
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one_s <= '1';
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one_s <= '1';
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p2_b <= (others => 'H');
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p2_b <= (others => 'H');
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p1_b <= (others => 'H');
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p1_b <= (others => 'H');
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-----------------------------------------------------------------------------
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-- External ROM, 3k bytes
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-- Initialized by file t48_ext_rom.hex.
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-----------------------------------------------------------------------------
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ext_rom_b : lpm_rom
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generic map (
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LPM_WIDTH => 8,
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LPM_TYPE => "LPM_ROM",
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LPM_WIDTHAD => 12,
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LPM_NUMWORDS => 3 * (2 ** 10),
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LPM_FILE => "rom_t48_ext.hex",
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LPM_ADDRESS_CONTROL => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_HINT => "UNUSED"
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)
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port map (
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address => ext_mem_addr_s,
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inclock => xtal_s,
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outclock => zero_s, -- unused
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memenab => one_s,
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q => ext_rom_data_s
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);
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ext_ram_b : generic_ram_ena
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ext_ram_b : generic_ram_ena
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generic map (
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generic map (
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addr_width_g => 8,
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addr_width_g => 8,
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data_width_g => 8
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data_width_g => 8
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)
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)
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port map (
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port map (
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clk_i => zero_s,
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clk_i => xtal_s,
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a_i => ext_ram_addr_s,
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a_i => ext_mem_addr_s(7 downto 0),
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we_i => ext_ram_we_s,
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we_i => ext_ram_we_s,
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ena_i => one_s,
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ena_i => one_s,
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d_i => db_b,
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d_i => db_b,
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d_o => ext_ram_data_from_s
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d_o => ext_ram_data_from_s
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);
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);
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p1_b => p1_b,
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p1_b => p1_b,
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prog_n_o => prog_n_s
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prog_n_o => prog_n_s
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);
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);
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-----------------------------------------------------------------------------
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-- Read from external memory
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--
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db_b <= ext_rom_data_s
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when psen_n_s = '0' else
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(others => 'Z');
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db_b <= ext_ram_data_from_s
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when rd_n_s = '0' else
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(others => 'Z');
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- External RAM access signals
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-- External RAM access signals
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--
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--
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ext_ram: process (wr_n_s,
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ext_ram: process (wr_n_s,
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ale_s,
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ale_s,
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p2_b,
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db_b)
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db_b)
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begin
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begin
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ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
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if ale_s'event and ale_s = '0' then
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if ale_s'event and ale_s = '0' then
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if not is_X(db_b) then
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if not is_X(db_b) then
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ext_ram_addr_s <= db_b;
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ext_mem_addr_s(7 downto 0) <= db_b;
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else
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else
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ext_ram_addr_s <= (others => '0');
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ext_mem_addr_s(7 downto 0) <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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if wr_n_s'event and wr_n_s = '1' then
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if wr_n_s'event and wr_n_s = '1' then
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ext_ram_we_s <= '0';
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end if;
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if wr_n_s'event and wr_n_s = '0' then
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ext_ram_we_s <= '1';
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ext_ram_we_s <= '1';
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end if;
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end if;
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-- if clk_s'event then
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-- ext_ram_we_s <= '0';
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-- end if;
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end process ext_ram;
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end process ext_ram;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.5 2006/06/21 01:04:05 arniml
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-- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom
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--
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-- Revision 1.4 2004/04/18 19:00:58 arniml
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-- Revision 1.4 2004/04/18 19:00:58 arniml
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-- connect T0 and T1 to P1
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-- connect T0 and T1 to P1
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--
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--
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-- Revision 1.3 2004/04/14 20:57:44 arniml
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-- Revision 1.3 2004/04/14 20:57:44 arniml
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-- wait for instruction strobe after final end-of-simulation detection
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-- wait for instruction strobe after final end-of-simulation detection
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