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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Clock Control unit.
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-- The Clock Control unit.
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-- Clock States and Machine Cycles are generated here.
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-- Clock States and Machine Cycles are generated here.
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--
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--
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-- $Id: clock_ctrl.vhd,v 1.6 2004-10-25 20:31:12 arniml Exp $
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-- $Id: clock_ctrl.vhd,v 1.7 2005-05-04 20:12:36 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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Line 60... |
clk_i : in std_logic;
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clk_i : in std_logic;
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xtal_i : in std_logic;
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xtal_i : in std_logic;
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res_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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en_clk_i : in boolean;
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xtal3_o : out boolean;
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xtal3_o : out boolean;
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t0_o : out std_logic;
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multi_cycle_i : in boolean;
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multi_cycle_i : in boolean;
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assert_psen_i : in boolean;
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assert_psen_i : in boolean;
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assert_prog_i : in boolean;
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assert_prog_i : in boolean;
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assert_rd_i : in boolean;
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assert_rd_i : in boolean;
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assert_wr_i : in boolean;
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assert_wr_i : in boolean;
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Line 92... |
xtal3_s : boolean;
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xtal3_s : boolean;
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signal x1_s,
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signal x1_s,
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x2_s,
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x2_s,
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x3_s : std_logic;
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x3_s : std_logic;
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signal t0_q : std_logic;
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-- The five clock states.
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-- The five clock states.
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signal mstate_q : mstate_t;
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signal mstate_q : mstate_t;
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signal ale_q : boolean;
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signal ale_q : boolean;
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use_xtal_div: if xtal_div_3_g = 1 generate
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use_xtal_div: if xtal_div_3_g = 1 generate
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xtal: process (res_i, xtal_i)
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xtal: process (res_i, xtal_i)
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begin
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begin
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if res_i = res_active_c then
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if res_i = res_active_c then
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xtal_q <= TO_UNSIGNED(0, 2);
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xtal_q <= TO_UNSIGNED(0, 2);
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t0_q <= '0';
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elsif xtal_i'event and xtal_i = clk_active_c then
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elsif xtal_i'event and xtal_i = clk_active_c then
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if xtal_q < 2 then
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if xtal_q < 2 then
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xtal_q <= xtal_q + 1;
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xtal_q <= xtal_q + 1;
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else
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else
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xtal_q <= TO_UNSIGNED(0, 2);
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xtal_q <= TO_UNSIGNED(0, 2);
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end if;
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end if;
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if xtal3_s then
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t0_q <= '1';
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else
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t0_q <= '0';
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end if;
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end if;
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end if;
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end process xtal;
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end process xtal;
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x1_s <= '1'
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x1_s <= '1'
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Line 161... |
when xtal_q = 1 else
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when xtal_q = 1 else
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'0';
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'0';
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x3_s <= '1'
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x3_s <= '1'
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when xtal_q = 2 else
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when xtal_q = 2 else
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'0';
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'0';
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t0_o <= t0_q;
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end generate;
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end generate;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- XTAL1 is used directly for Clock States.
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-- XTAL1 is used directly for Clock States.
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Line 174... |
xtal_q <= TO_UNSIGNED(0, 2);
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xtal_q <= TO_UNSIGNED(0, 2);
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x1_s <= '1';
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x1_s <= '1';
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x2_s <= '1';
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x2_s <= '1';
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x3_s <= '1';
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x3_s <= '1';
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t0_o <= xtal_i;
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end generate;
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end generate;
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-- And finally the boolean flags --------------------------------------------
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-- And finally the boolean flags --------------------------------------------
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xtal1_s <= to_boolean(x1_s);
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xtal1_s <= to_boolean(x1_s);
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Line 396... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.6 2004/10/25 20:31:12 arniml
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-- remove PROG and end of XTAL2, see comment for details
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--
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-- Revision 1.5 2004/10/25 19:35:41 arniml
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-- Revision 1.5 2004/10/25 19:35:41 arniml
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-- deassert rd_q, wr_q and prog_q at end of XTAL3
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-- deassert rd_q, wr_q and prog_q at end of XTAL3
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--
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--
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-- Revision 1.4 2004/04/24 23:44:25 arniml
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-- Revision 1.4 2004/04/24 23:44:25 arniml
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-- move from std_logic_arith to numeric_std
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-- move from std_logic_arith to numeric_std
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