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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Clock Control unit.
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-- The Clock Control unit.
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-- Clock States and Machine Cycles are generated here.
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-- Clock States and Machine Cycles are generated here.
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--
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--
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-- $Id: clock_ctrl.vhd,v 1.7 2005-05-04 20:12:36 arniml Exp $
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-- $Id: clock_ctrl.vhd,v 1.8 2005-06-09 22:15:10 arniml Exp $
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--
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--
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-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 214... |
Line 214... |
wr_q <= true;
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wr_q <= true;
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end if;
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end if;
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end if;
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end if;
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when MSTATE1 =>
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when MSTATE1 =>
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if xtal3_s then
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if en_clk_i then -- equivalent to xtal3_s
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psen_q <= false;
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psen_q <= false;
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end if;
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end if;
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when MSTATE2 =>
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when MSTATE2 =>
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if xtal2_s then
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if xtal2_s then
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Line 227... |
-- end of XTAL3 but this would raise the need to change P2 at
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-- end of XTAL3 but this would raise the need to change P2 at
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-- XTAL1 or XTAL2 -> introduction of inter-xtal timing in
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-- XTAL1 or XTAL2 -> introduction of inter-xtal timing in
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-- the rest of the core.
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-- the rest of the core.
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prog_q <= false;
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prog_q <= false;
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end if;
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end if;
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if xtal3_s then
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if en_clk_i then -- equivalent to xtal3_s
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-- RD, WR are removed at the end of XTAL3 of second machine cycle
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-- RD, WR are removed at the end of XTAL3 of second machine cycle
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rd_q <= false;
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rd_q <= false;
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wr_q <= false;
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wr_q <= false;
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end if;
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end if;
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| Line 240... |
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if xtal2_s then
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if xtal2_s then
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ale_q <= true;
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ale_q <= true;
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end if;
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end if;
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when MSTATE4 =>
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when MSTATE4 =>
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if xtal3_s then
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if en_clk_i then -- equivalent to xtal3_s
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-- PSEN is set at the end of XTAL3
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-- PSEN is set at the end of XTAL3
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if assert_psen_i then
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if assert_psen_i then
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psen_q <= true;
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psen_q <= true;
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end if;
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end if;
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| Line 396... |
Line 396... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.7 2005/05/04 20:12:36 arniml
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-- Fix bug report:
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-- "Wrong clock applied to T0"
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-- t0_o is generated inside clock_ctrl with a separate flip-flop running
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-- with xtal_i
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--
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-- Revision 1.6 2004/10/25 20:31:12 arniml
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-- Revision 1.6 2004/10/25 20:31:12 arniml
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-- remove PROG and end of XTAL2, see comment for details
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-- remove PROG and end of XTAL2, see comment for details
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--
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--
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-- Revision 1.5 2004/10/25 19:35:41 arniml
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-- Revision 1.5 2004/10/25 19:35:41 arniml
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-- deassert rd_q, wr_q and prog_q at end of XTAL3
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-- deassert rd_q, wr_q and prog_q at end of XTAL3
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| Line 415... |
Line 421... |
-- move code for PROG out of if-branch for xtal3_s
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-- move code for PROG out of if-branch for xtal3_s
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--
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--
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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-- initial check-in
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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