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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [clock_ctrl.vhd] - Diff between revs 219 and 249

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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- The Clock Control unit.
-- The Clock Control unit.
-- Clock States and Machine Cycles are generated here.
-- Clock States and Machine Cycles are generated here.
--
--
-- $Id: clock_ctrl.vhd,v 1.11 2006-06-20 00:46:38 arniml Exp $
-- $Id: clock_ctrl.vhd,v 1.12 2006-07-14 01:04:35 arniml Exp $
--
--
-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved
-- All rights reserved
--
--
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          if xtal3_s then
          if xtal3_s then
             psen_q   <= false;
             psen_q   <= false;
           end if;
           end if;
 
 
        when MSTATE2 =>
        when MSTATE2 =>
          if xtal2_s then
 
            -- PROG is removed at the end of XTAL2 of second machine cycle
 
            -- according to the user manual, PROG should be removed at the
 
            -- end of XTAL3 but this would raise the need to change P2 at
 
            -- XTAL1 or XTAL2 -> introduction of inter-xtal timing in
 
            -- the rest of the core.
 
            prog_q   <= false;
 
          end if;
 
          if xtal3_s then
          if xtal3_s then
            -- RD, WR are removed at the end of XTAL3 of second machine cycle
            -- RD, WR are removed at the end of XTAL3 of second machine cycle
            rd_q     <= false;
            rd_q     <= false;
            wr_q     <= false;
            wr_q     <= false;
 
            -- so is PROG
 
            prog_q   <= false;
          end if;
          end if;
 
 
        when MSTATE3 =>
        when MSTATE3 =>
          -- ALE is set at the end of XTAL3 of every machine cycle
          -- ALE is set at the end of XTAL3 of every machine cycle
          if xtal3_s then
          if xtal3_s then
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.11  2006/06/20 00:46:38  arniml
 
-- new input xtal_en_i gates xtal_i base clock
 
--
-- Revision 1.10  2005/11/01 21:24:21  arniml
-- Revision 1.10  2005/11/01 21:24:21  arniml
-- * shift assertion of ALE and PROG to xtal3
-- * shift assertion of ALE and PROG to xtal3
-- * correct change of revision 1.8
-- * correct change of revision 1.8
--
--
-- Revision 1.9  2005/06/11 10:08:43  arniml
-- Revision 1.9  2005/06/11 10:08:43  arniml

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