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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The BUS unit.
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-- The BUS unit.
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-- Implements the BUS port logic.
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-- Implements the BUS port logic.
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--
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--
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-- $Id: db_bus.vhd,v 1.4 2005-06-09 22:16:26 arniml Exp $
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-- $Id: db_bus.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_t;
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use work.t48_pack.word_t;
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entity db_bus is
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entity t48_db_bus is
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port (
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port (
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-- Global Interface -------------------------------------------------------
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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clk_i : in std_logic;
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res_i : in std_logic;
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res_i : in std_logic;
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db_i : in word_t;
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db_i : in word_t;
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db_o : out word_t;
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db_o : out word_t;
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db_dir_o : out std_logic
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db_dir_o : out std_logic
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);
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);
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end db_bus;
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end t48_db_bus;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.to_stdLogic;
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use work.t48_pack.to_stdLogic;
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architecture rtl of db_bus is
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architecture rtl of t48_db_bus is
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-- the BUS output register
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-- the BUS output register
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signal bus_q : word_t;
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signal bus_q : word_t;
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-- BUS direction marker
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-- BUS direction marker
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2005/06/09 22:16:26 arniml
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-- Implement db_dir_o glitch-safe
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--
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-- Revision 1.3 2004/10/25 20:30:18 arniml
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-- Revision 1.3 2004/10/25 20:30:18 arniml
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-- delay db_dir_o by one machine cycle
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-- delay db_dir_o by one machine cycle
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-- this fixes the timing relation between BUS data and WR'
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-- this fixes the timing relation between BUS data and WR'
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--
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--
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-- Revision 1.2 2004/04/04 14:15:45 arniml
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-- Revision 1.2 2004/04/04 14:15:45 arniml
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