| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The BUS unit.
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-- The BUS unit.
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-- Implements the BUS port logic.
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-- Implements the BUS port logic.
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--
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--
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-- $Id: db_bus.vhd,v 1.1 2004-03-23 21:31:52 arniml Exp $
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-- $Id: db_bus.vhd,v 1.2 2004-04-04 14:15:45 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 96... |
Line 96... |
-- Implements the BUS output register.
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-- Implements the BUS output register.
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--
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--
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bus_regs: process (res_i, clk_i)
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bus_regs: process (res_i, clk_i)
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begin
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begin
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if res_i = res_active_c then
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if res_i = res_active_c then
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bus_q <= (others => '1');
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bus_q <= (others => '0');
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db_dir_q <= '0';
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db_dir_q <= '0';
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|
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elsif clk_i'event and clk_i = clk_active_c then
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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if en_clk_i then
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| Line 139... |
Line 139... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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