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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Decoder unit.
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-- The Decoder unit.
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-- It decodes the instruction opcodes and executes them.
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-- It decodes the instruction opcodes and executes them.
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--
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--
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-- $Id: decoder.vhd,v 1.10 2004-04-25 16:22:03 arniml Exp $
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-- $Id: decoder.vhd,v 1.11 2004-05-16 15:33:39 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 171... |
Line 171... |
use work.t48_tb_pack.tb_istrobe_s;
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use work.t48_tb_pack.tb_istrobe_s;
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-- pragma translate_on
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-- pragma translate_on
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architecture rtl of decoder is
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architecture rtl of decoder is
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-- Enable fixing a bug of Quartus II 4.0
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constant enable_quartus_bugfix_c : boolean := true;
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-- Opcode Decoder
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-- Opcode Decoder
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signal opc_multi_cycle_s : boolean;
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signal opc_multi_cycle_s : boolean;
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signal opc_read_bus_s : boolean;
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signal opc_read_bus_s : boolean;
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signal opc_inj_int_s : boolean;
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signal opc_inj_int_s : boolean;
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signal opc_opcode_s : word_t;
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signal opc_opcode_s : word_t;
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| Line 404... |
Line 407... |
int_pending_s)
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int_pending_s)
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procedure address_indirect_3_f is
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procedure address_indirect_3_f is
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begin
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begin
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-- apply dmem address from selected register for indirect mode
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-- apply dmem address from selected register for indirect mode
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if opc_opcode_s(3) = '0' then
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if opc_opcode_s(3) = '0' or enable_quartus_bugfix_c then
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dm_read_dmem_o <= true;
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dm_read_dmem_o <= true;
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dm_write_dmem_addr_o <= true;
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dm_write_dmem_addr_o <= true;
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dm_addr_type_o <= DM_PLAIN;
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dm_addr_type_o <= DM_PLAIN;
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end if;
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end if;
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end;
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end;
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| Line 430... |
Line 433... |
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procedure cond_jump_c2_m1_f is
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procedure cond_jump_c2_m1_f is
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begin
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begin
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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-- if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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pm_write_pcl_o <= true;
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pm_write_pcl_o <= true;
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branch_taken_s <= true;
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branch_taken_s <= true;
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end if;
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-- end if;
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end;
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end;
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begin
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begin
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-- default assignments
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-- default assignments
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data_s <= (others => '-');
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data_s <= (others => '-');
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| Line 532... |
Line 535... |
-- Mnemonic ADD ---------------------------------------------------------
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-- Mnemonic ADD ---------------------------------------------------------
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when MN_ADD =>
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when MN_ADD =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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-- store data from RAM to Temp Reg
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-- store data from RAM to Temp Reg
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when MSTATE4 =>
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when MSTATE4 =>
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and_or_xor_add_4_f;
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and_or_xor_add_4_f;
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| Line 589... |
Line 595... |
-- Mnemonic ANL ---------------------------------------------------------
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-- Mnemonic ANL ---------------------------------------------------------
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when MN_ANL =>
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when MN_ANL =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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-- store data from RAM to Temp Reg
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-- store data from RAM to Temp Reg
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when MSTATE4 =>
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when MSTATE4 =>
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and_or_xor_add_4_f;
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and_or_xor_add_4_f;
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| Line 932... |
Line 941... |
end case;
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end case;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic ENT0_CLK ----------------------------------------------------
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-- Mnemonic ENT0_CLK ----------------------------------------------------
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when MN_ENT0_CLK =>
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when MN_ENT0_CLK =>
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| Line 969... |
Line 980... |
-- Mnemonic INC ---------------------------------------------------------
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-- Mnemonic INC ---------------------------------------------------------
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when MN_INC =>
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when MN_INC =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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when MSTATE4 =>
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when MSTATE4 =>
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-- INC Rr; INC @ Rr: store data from RAM to shadow Accumulator
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-- INC Rr; INC @ Rr: store data from RAM to shadow Accumulator
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if opc_opcode_s(3 downto 2) /= "01" then
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if opc_opcode_s(3 downto 2) /= "01" then
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dm_read_dmem_o <= true;
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dm_read_dmem_o <= true;
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| Line 1011... |
Line 1025... |
end if;
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end if;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic JC ----------------------------------------------------------
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-- Mnemonic JC ----------------------------------------------------------
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when MN_JC =>
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when MN_JC =>
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| Line 1030... |
Line 1046... |
end if;
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end if;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic JF ----------------------------------------------------------
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-- Mnemonic JF ----------------------------------------------------------
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when MN_JF =>
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when MN_JF =>
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| Line 1055... |
Line 1073... |
end if;
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end if;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic JMP ---------------------------------------------------------
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-- Mnemonic JMP ---------------------------------------------------------
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| Line 1120... |
Line 1140... |
end if;
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end if;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic JT ----------------------------------------------------------
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-- Mnemonic JT ----------------------------------------------------------
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when MN_JT =>
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when MN_JT =>
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| Line 1143... |
Line 1165... |
end if;
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end if;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic JTF ---------------------------------------------------------
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-- Mnemonic JTF ---------------------------------------------------------
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when MN_JTF =>
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when MN_JTF =>
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| Line 1162... |
Line 1186... |
end if;
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end if;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic JZ ----------------------------------------------------------
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-- Mnemonic JZ ----------------------------------------------------------
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when MN_JZ =>
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when MN_JZ =>
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| Line 1182... |
Line 1208... |
end if;
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end if;
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else
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else
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-- store address in Program Counter low byte if branch has to
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-- store address in Program Counter low byte if branch has to
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-- be taken
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-- be taken
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if clk_mstate_i = MSTATE1 and cnd_take_branch_i then
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cond_jump_c2_m1_f;
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cond_jump_c2_m1_f;
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end if;
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end if;
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end if;
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-- Mnemonic MOV_A_DATA --------------------------------------------------
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-- Mnemonic MOV_A_DATA --------------------------------------------------
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when MN_MOV_A_DATA =>
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when MN_MOV_A_DATA =>
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| Line 1201... |
Line 1229... |
-- Mnemonic MOV_A_RR ----------------------------------------------------
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-- Mnemonic MOV_A_RR ----------------------------------------------------
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when MN_MOV_A_RR =>
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when MN_MOV_A_RR =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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-- read data from RAM and store in Accumulator
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-- read data from RAM and store in Accumulator
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when MSTATE4 =>
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when MSTATE4 =>
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and_or_xor_add_4_f;
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and_or_xor_add_4_f;
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alu_write_accu_o <= true;
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alu_write_accu_o <= true;
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| Line 1234... |
Line 1265... |
-- Mnemonic MOV_RR ------------------------------------------------------
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-- Mnemonic MOV_RR ------------------------------------------------------
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when MN_MOV_RR =>
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when MN_MOV_RR =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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-- write Accumulator to dmem
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-- write Accumulator to dmem
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when MSTATE5 =>
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when MSTATE5 =>
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alu_read_alu_o <= true;
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alu_read_alu_o <= true;
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dm_write_dmem_s <= true;
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dm_write_dmem_s <= true;
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| Line 1252... |
Line 1286... |
when MN_MOV_RR_DATA =>
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when MN_MOV_RR_DATA =>
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assert_psen_s <= true;
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assert_psen_s <= true;
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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if not clk_second_cycle_i and clk_mstate_i = MSTATE3 then
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if not clk_second_cycle_i and clk_mstate_i = MSTATE3 then
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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end if;
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end if;
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-- Write Data Memory when contents of Program Memory is on bus
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-- Write Data Memory when contents of Program Memory is on bus
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-- during machine state 1 of second cycle.
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-- during machine state 1 of second cycle.
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if clk_second_cycle_i and clk_mstate_i = MSTATE1 then
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if clk_second_cycle_i and clk_mstate_i = MSTATE1 then
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dm_write_dmem_s <= true;
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dm_write_dmem_s <= true;
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| Line 1453... |
Line 1490... |
-- Mnemonic ORL ---------------------------------------------------------
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-- Mnemonic ORL ---------------------------------------------------------
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when MN_ORL =>
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when MN_ORL =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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-- store data from RAM to Temp Reg
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-- store data from RAM to Temp Reg
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when MSTATE4 =>
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when MSTATE4 =>
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and_or_xor_add_4_f;
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and_or_xor_add_4_f;
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| Line 1685... |
Line 1725... |
-- Mnemonic XCH ---------------------------------------------------------
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-- Mnemonic XCH ---------------------------------------------------------
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when MN_XCH =>
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when MN_XCH =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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-- store data from RAM in Accumulator and Temp Reg
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-- store data from RAM in Accumulator and Temp Reg
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-- Accumulator is already shadowed!
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-- Accumulator is already shadowed!
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when MSTATE4 =>
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when MSTATE4 =>
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dm_read_dmem_o <= true;
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dm_read_dmem_o <= true;
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| Line 1719... |
Line 1762... |
-- Mnemonic XRL ---------------------------------------------------------
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-- Mnemonic XRL ---------------------------------------------------------
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when MN_XRL =>
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when MN_XRL =>
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case clk_mstate_i is
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case clk_mstate_i is
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-- read RAM once for indirect address mode
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-- read RAM once for indirect address mode
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when MSTATE3 =>
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when MSTATE3 =>
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if not enable_quartus_bugfix_c or
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opc_opcode_s(3) = '0' then
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address_indirect_3_f;
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address_indirect_3_f;
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end if;
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-- store data from RAM to Temp Reg
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-- store data from RAM to Temp Reg
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when MSTATE4 =>
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when MSTATE4 =>
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and_or_xor_add_4_f;
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and_or_xor_add_4_f;
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| Line 1883... |
Line 1929... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.10 2004/04/25 16:22:03 arniml
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-- adjust external timing of BUS
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--
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-- Revision 1.9 2004/04/24 11:22:55 arniml
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-- Revision 1.9 2004/04/24 11:22:55 arniml
|
-- removed superfluous signal from sensitivity list
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-- removed superfluous signal from sensitivity list
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--
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--
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-- Revision 1.8 2004/04/18 18:57:43 arniml
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-- Revision 1.8 2004/04/18 18:57:43 arniml
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-- + enhance instruction strobe generation
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-- + enhance instruction strobe generation
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