| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Interrupt Controller.
|
-- The Interrupt Controller.
|
-- It collects the interrupt sources and notifies the decoder.
|
-- It collects the interrupt sources and notifies the decoder.
|
--
|
--
|
-- $Id: int.vhd,v 1.1 2004-03-23 21:31:52 arniml Exp $
|
-- $Id: int.vhd,v 1.2 2004-06-30 21:18:28 arniml Exp $
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
| Line 66... |
Line 66... |
dis_i_i : in boolean;
|
dis_i_i : in boolean;
|
ext_int_o : out boolean;
|
ext_int_o : out boolean;
|
tim_int_o : out boolean;
|
tim_int_o : out boolean;
|
retr_executed_i : in boolean;
|
retr_executed_i : in boolean;
|
int_executed_i : in boolean;
|
int_executed_i : in boolean;
|
int_pending_o : out boolean
|
int_pending_o : out boolean;
|
|
int_in_progress_o : out boolean
|
);
|
);
|
|
|
end int;
|
end int;
|
|
|
|
|
| Line 143... |
Line 144... |
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process regs
|
-- Process regs
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Implement the various registers.
|
-- Implement the various registers.
|
|
-- They are designed according Figure "Interrupt Logic" of
|
|
-- "The Single Component MCS-48 System".
|
--
|
--
|
regs: process (res_i, clk_i)
|
regs: process (res_i, clk_i)
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
timer_flag_q <= false;
|
timer_flag_q <= false;
|
| Line 220... |
Line 223... |
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
tf_o <= to_stdLogic(timer_flag_q);
|
tf_o <= to_stdLogic(timer_flag_q);
|
ext_int_o <= int_type_q = ext_int_c;
|
ext_int_o <= int_type_q = ext_int_c;
|
tim_int_o <= int_type_q = tim_int_c;
|
tim_int_o <= int_type_q = tim_int_c;
|
int_pending_o <= int_state_q = PENDING;
|
int_pending_o <= int_state_q = PENDING;
|
|
int_in_progress_o <= int_in_progress_q;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
|
-- initial check-in
|
|
--
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
