| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Port 2 unit.
|
-- The Port 2 unit.
|
-- Implements the Port 2 logic.
|
-- Implements the Port 2 logic.
|
--
|
--
|
-- $Id: p2.vhd,v 1.6 2004-07-11 16:51:33 arniml Exp $
|
-- $Id: p2.vhd,v 1.7 2005-06-11 10:08:43 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
| Line 48... |
Line 48... |
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
use work.t48_pack.word_t;
|
use work.t48_pack.word_t;
|
use work.t48_pack.nibble_t;
|
use work.t48_pack.nibble_t;
|
|
|
entity p2 is
|
entity t48_p2 is
|
|
|
port (
|
port (
|
-- Global Interface -------------------------------------------------------
|
-- Global Interface -------------------------------------------------------
|
clk_i : in std_logic;
|
clk_i : in std_logic;
|
res_i : in std_logic;
|
res_i : in std_logic;
|
| Line 72... |
Line 72... |
p2_i : in word_t;
|
p2_i : in word_t;
|
p2_o : out word_t;
|
p2_o : out word_t;
|
p2_low_imp_o : out std_logic
|
p2_low_imp_o : out std_logic
|
);
|
);
|
|
|
end p2;
|
end t48_p2;
|
|
|
|
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.bus_idle_level_c;
|
|
|
architecture rtl of p2 is
|
architecture rtl of t48_p2 is
|
|
|
-- the port output register
|
-- the port output register
|
signal p2_q : word_t;
|
signal p2_q : word_t;
|
|
|
-- the low impedance marker
|
-- the low impedance marker
|
| Line 196... |
Line 196... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.6 2004/07/11 16:51:33 arniml
|
|
-- cleanup copyright notice
|
|
--
|
-- Revision 1.5 2004/05/17 13:52:46 arniml
|
-- Revision 1.5 2004/05/17 13:52:46 arniml
|
-- Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"
|
-- Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"
|
--
|
--
|
-- Revision 1.4 2004/04/24 23:44:25 arniml
|
-- Revision 1.4 2004/04/24 23:44:25 arniml
|
-- move from std_logic_arith to numeric_std
|
-- move from std_logic_arith to numeric_std
|
