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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [p2.vhd] - Diff between revs 206 and 220

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Line 1... Line 1...
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- The Port 2 unit.
-- The Port 2 unit.
-- Implements the Port 2 logic.
-- Implements the Port 2 logic.
--
--
-- $Id: p2.vhd,v 1.8 2005-11-01 21:27:55 arniml Exp $
-- $Id: p2.vhd,v 1.9 2006-06-20 00:46:04 arniml Exp $
--
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved
-- All rights reserved
--
--
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    -- Global Interface -------------------------------------------------------
    -- Global Interface -------------------------------------------------------
    clk_i         : in  std_logic;
    clk_i         : in  std_logic;
    res_i         : in  std_logic;
    res_i         : in  std_logic;
    en_clk_i      : in  boolean;
    en_clk_i      : in  boolean;
    xtal_i        : in  std_logic;
    xtal_i        : in  std_logic;
 
    xtal_en_i     : in  boolean;
    -- T48 Bus Interface ------------------------------------------------------
    -- T48 Bus Interface ------------------------------------------------------
    data_i        : in  word_t;
    data_i        : in  word_t;
    data_o        : out word_t;
    data_o        : out word_t;
    write_p2_i    : in  boolean;
    write_p2_i    : in  boolean;
    write_exp_i   : in  boolean;
    write_exp_i   : in  boolean;
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      h_low_imp_del_q <= '0';
      h_low_imp_del_q <= '0';
      output_pch_q    <= false;
      output_pch_q    <= false;
      en_clk_q        <= false;
      en_clk_q        <= false;
 
 
    elsif xtal_i'event and xtal_i = clk_active_c then
    elsif xtal_i'event and xtal_i = clk_active_c then
 
      if xtal_en_i then
      -- delay clock enable by one XTAL period
      -- delay clock enable by one XTAL period
      en_clk_q               <= en_clk_i;
      en_clk_q               <= en_clk_i;
 
 
      p2_o                   <= p2_q;
      p2_o                   <= p2_q;
      output_pch_q           <= output_pch_i;
      output_pch_q           <= output_pch_i;
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      else
      else
        h_low_imp_del_q <= '0';
        h_low_imp_del_q <= '0';
      end if;
      end if;
 
 
    end if;
    end if;
 
    end if;
  end process p2_port;
  end process p2_port;
  --
  --
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
 
 
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.8  2005/11/01 21:27:55  arniml
 
-- * change low impedance markers for P2
 
--   separate marker for low and high part
 
-- * p2_o output is also registered to prevent combinational
 
--   output to pads
 
--
-- Revision 1.7  2005/06/11 10:08:43  arniml
-- Revision 1.7  2005/06/11 10:08:43  arniml
-- introduce prefix 't48_' for all packages, entities and configurations
-- introduce prefix 't48_' for all packages, entities and configurations
--
--
-- Revision 1.6  2004/07/11 16:51:33  arniml
-- Revision 1.6  2004/07/11 16:51:33  arniml
-- cleanup copyright notice
-- cleanup copyright notice

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