| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Port 2 unit.
|
-- The Port 2 unit.
|
-- Implements the Port 2 logic.
|
-- Implements the Port 2 logic.
|
--
|
--
|
-- $Id: p2.vhd,v 1.2 2004-03-28 13:11:43 arniml Exp $
|
-- $Id: p2.vhd,v 1.3 2004-03-29 19:39:58 arniml Exp $
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
| Line 67... |
Line 67... |
output_pch_i : in boolean;
|
output_pch_i : in boolean;
|
output_exp_i : in boolean;
|
output_exp_i : in boolean;
|
pch_i : in nibble_t;
|
pch_i : in nibble_t;
|
p2_i : in word_t;
|
p2_i : in word_t;
|
p2_o : out word_t;
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p2_o : out word_t;
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p2_limp_o : out std_logic
|
p2_low_imp_o : out std_logic
|
);
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);
|
|
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end p2;
|
end p2;
|
|
|
|
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| Line 87... |
Line 87... |
|
|
-- the port output register
|
-- the port output register
|
signal p2_q : word_t;
|
signal p2_q : word_t;
|
|
|
-- the low impedance marker
|
-- the low impedance marker
|
signal limp_q : std_logic;
|
signal low_imp_q : std_logic;
|
|
|
-- the expander register
|
-- the expander register
|
signal exp_q : nibble_t;
|
signal exp_q : nibble_t;
|
|
|
begin
|
begin
|
| Line 104... |
Line 104... |
--
|
--
|
p2_regs: process (res_i, clk_i)
|
p2_regs: process (res_i, clk_i)
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
p2_q <= (others => '1');
|
p2_q <= (others => '1');
|
limp_q <= '0';
|
low_imp_q <= '0';
|
exp_q <= (others => '0');
|
exp_q <= (others => '0');
|
|
|
elsif clk_i'event and clk_i = clk_active_c then
|
elsif clk_i'event and clk_i = clk_active_c then
|
if en_clk_i then
|
if en_clk_i then
|
|
|
if write_p2_i then
|
if write_p2_i then
|
p2_q <= data_i;
|
p2_q <= data_i;
|
limp_q <= '1';
|
low_imp_q <= '1';
|
else
|
else
|
limp_q <= '0';
|
low_imp_q <= '0';
|
end if;
|
end if;
|
|
|
if write_exp_i then
|
if write_exp_i then
|
exp_q <= data_i(exp_q'range);
|
exp_q <= data_i(exp_q'range);
|
end if;
|
end if;
|
| Line 187... |
Line 187... |
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Output Mapping.
|
-- Output Mapping.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
p2_limp_o <= limp_q;
|
p2_low_imp_o <= low_imp_q;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2004/03/28 13:11:43 arniml
|
|
-- rework Port 2 expander handling
|
|
--
|
-- Revision 1.1 2004/03/23 21:31:53 arniml
|
-- Revision 1.1 2004/03/23 21:31:53 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
