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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [lpm_rom.vhd] - Diff between revs 7 and 77

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Rev 7 Rev 77
Line 95... Line 95...
--    string "UNUSED".
--    string "UNUSED".
--------------------------------------------------------------------------
--------------------------------------------------------------------------
 
 
library IEEE;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
 
--use work.LPM_COMPONENTS.all;
--use work.LPM_COMPONENTS.all;
use std.textio.all;
use std.textio.all;
 
 
entity LPM_ROM is
entity LPM_ROM is
        generic (LPM_WIDTH : positive;
        generic (LPM_WIDTH : positive;
Line 288... Line 287...
        variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
        variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
        variable startadd: string(4 downto 1);
        variable startadd: string(4 downto 1);
        variable ibase: integer := 0;
        variable ibase: integer := 0;
        variable ibyte: integer := 0;
        variable ibyte: integer := 0;
        variable istartadd: integer := 0;
        variable istartadd: integer := 0;
        variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
        variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0);
        begin
        begin
                -- INITIALIZE --
                -- INITIALIZE --
                if NOT(mem_init) then
                if NOT(mem_init) then
                        -- INITIALIZE TO 0 --
                        -- INITIALIZE TO 0 --
                        for i in mem_data'LOW to mem_data'HIGH loop
                        for i in mem_data'LOW to mem_data'HIGH loop
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                                                        ASSERT FALSE
                                                        ASSERT FALSE
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
                                                        SEVERITY ERROR;
                                                        SEVERITY ERROR;
                                                end if;
                                                end if;
                                                ibyte := hex_str_to_int(byte);
                                                ibyte := hex_str_to_int(byte);
                                                check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
                                                check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, 8);
                                                READ(L=>buf, VALUE=>startadd, good=>booval);
                                                READ(L=>buf, VALUE=>startadd, good=>booval);
                                                if not (booval) then
                                                if not (booval) then
                                                        ASSERT FALSE
                                                        ASSERT FALSE
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                        SEVERITY ERROR;
                                                        SEVERITY ERROR;
                                                end if;
                                                end if;
                                                istartadd := hex_str_to_int(startadd);
                                                istartadd := hex_str_to_int(startadd);
                                                addr(2) := startadd(4);
                                                addr(2) := startadd(4);
                                                addr(1) := startadd(3);
                                                addr(1) := startadd(3);
                                                check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(hex_str_to_int(addr), 8));
                                                check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
                                                addr(2) := startadd(2);
                                                addr(2) := startadd(2);
                                                addr(1) := startadd(1);
                                                addr(1) := startadd(1);
                                                check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(hex_str_to_int(addr), 8));
                                                check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
                                                READ(L=>buf, VALUE=>rec_type, good=>booval);
                                                READ(L=>buf, VALUE=>rec_type, good=>booval);
                                                if not (booval) then
                                                if not (booval) then
                                                        ASSERT FALSE
                                                        ASSERT FALSE
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                        SEVERITY ERROR;
                                                        SEVERITY ERROR;
                                                end if;
                                                end if;
                                                check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(hex_str_to_int(rec_type), 8));
                                                check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length);
                                        else
                                        else
                                                ASSERT FALSE
                                                ASSERT FALSE
                                                REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                SEVERITY ERROR;
                                                SEVERITY ERROR;
                                        end if;
                                        end if;
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                                                                        if not (booval) then
                                                                        if not (booval) then
                                                                                ASSERT FALSE
                                                                                ASSERT FALSE
                                                                                REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                                                REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                                                SEVERITY ERROR;
                                                                                SEVERITY ERROR;
                                                                        end if;
                                                                        end if;
                                                                        check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(hex_str_to_int(datain), 8));
                                                                        check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length);
                                                                        mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
                                                                        mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
                                                                end loop;
                                                                end loop;
                                                                i := i + k;
                                                                i := i + k;
                                                                mem_data(ibase + istartadd) := CONV_STD_LOGIC_VECTOR(mem_data_tmp, lpm_width);
                                                                mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width));
                                                                istartadd := istartadd + 1;
                                                                istartadd := istartadd + 1;
                                                        end loop;
                                                        end loop;
                                                when "01"=>
                                                when "01"=>
                                                        exit;
                                                        exit;
                                                when "02"=>
                                                when "02"=>
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                                                                if not (booval) then
                                                                if not (booval) then
                                                                        ASSERT FALSE
                                                                        ASSERT FALSE
                                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
                                                                        SEVERITY ERROR;
                                                                        SEVERITY ERROR;
                                                                end if;
                                                                end if;
                                                                check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(hex_str_to_int(base), 8));
                                                                check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length);
                                                        end loop;
                                                        end loop;
                                                        ibase := ibase * 16;
                                                        ibase := ibase * 16;
                                                when OTHERS =>
                                                when OTHERS =>
                                                        ASSERT FALSE
                                                        ASSERT FALSE
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
                                                        REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
Line 400... Line 399...
                                                REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
                                                REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
                                                SEVERITY ERROR;
                                                SEVERITY ERROR;
                                        end if;
                                        end if;
 
 
                                        check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
                                        check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
                                        check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(hex_str_to_int(checksum),8);
                                        check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum),8);
 
 
                                        if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
                                        if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
                                                ASSERT FALSE
                                                ASSERT FALSE
                                                REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
                                                REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
                                                SEVERITY ERROR;
                                                SEVERITY ERROR;
Line 414... Line 413...
                        mem_init := TRUE;
                        mem_init := TRUE;
                end if;
                end if;
 
 
                -- MEMORY FUNCTION --
                -- MEMORY FUNCTION --
                --if memenab = '1' then
                --if memenab = '1' then
                        q_tmp <= mem_data(conv_integer(address_tmp));
                        q_tmp <= mem_data(to_integer(UNSIGNED(address_tmp)));
                --else
                --else
                --    q_tmp <= (OTHERS => 'Z');
                --    q_tmp <= (OTHERS => 'Z');
                --end if;
                --end if;
        end process;
        end process;
 
 

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