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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- T8039 Microcontroller System
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-- T8039 Microcontroller System
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--
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--
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-- $Id: t8039.vhd,v 1.4 2005-11-01 21:37:45 arniml Exp $
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-- $Id: t8039.vhd,v 1.5 2005-11-02 23:41:43 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 126... |
Line 126... |
bidirs: process (t0_b, t0_s, t0_dir_s,
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bidirs: process (t0_b, t0_s, t0_dir_s,
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db_b, db_s, db_dir_s,
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db_b, db_s, db_dir_s,
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p1_b, p1_s, p1_low_imp_s,
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p1_b, p1_s, p1_low_imp_s,
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p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s)
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p2_b, p2_s, p2l_low_imp_s, p2h_low_imp_s)
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function open_collector_f(sig : std_logic) return std_logic is
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function port_bidir_f(port_value : in std_logic_vector;
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variable sig_v : std_logic;
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low_imp : in std_logic) return std_logic_vector is
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variable result_v : std_logic_vector(port_value'range);
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begin
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begin
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sig_v := 'Z';
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for idx in port_value'high downto port_value'low loop
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if low_imp = '1' then
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if sig = '0' then
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result_v(idx) := port_value(idx);
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sig_v := '0';
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elsif port_value(idx) = '0' then
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result_v(idx) := '0';
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else
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result_v(idx) := 'Z';
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end if;
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end if;
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end loop;
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return sig_v;
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return result_v;
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end;
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end;
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begin
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begin
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-- Test 0 -----------------------------------------------------------------
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-- Test 0 -----------------------------------------------------------------
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if t0_dir_s = '1' then
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if t0_dir_s = '1' then
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| Line 154... |
Line 159... |
else
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else
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db_b <= (others => 'Z');
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db_b <= (others => 'Z');
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end if;
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end if;
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-- Port 1 -----------------------------------------------------------------
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-- Port 1 -----------------------------------------------------------------
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for i in p1_b'range loop
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p1_b <= port_bidir_f(port_value => p1_s,
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p1_b(i) <= open_collector_f(p1_s(i));
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low_imp => p1_low_imp_s);
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end loop;
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-- if p1_low_imp_s = '1' then
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-- p1_b <= p1_s;
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-- else
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-- p1_b <= (others => 'Z');
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-- end if;
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-- Port 2 -----------------------------------------------------------------
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-- Port 2 -----------------------------------------------------------------
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for i in p2_b'range loop
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p2_b(3 downto 0) <= port_bidir_f(port_value => p2_s(3 downto 0),
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p2_b(i) <= open_collector_f(p2_s(i));
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low_imp => p2l_low_imp_s);
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end loop;
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p2_b(7 downto 4) <= port_bidir_f(port_value => p2_s(7 downto 4),
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-- if p2_low_imp_s = '1' then
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low_imp => p2h_low_imp_s);
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-- p2_b <= p2_b_s;
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-- else
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-- p2_b <= (others => 'Z');
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-- end if;
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end process bidirs;
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end process bidirs;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 184... |
Line 179... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2005/11/01 21:37:45 arniml
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-- wire signals for P2 low impedance marker issue
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--
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-- Revision 1.3 2004/12/03 19:43:12 arniml
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-- Revision 1.3 2004/12/03 19:43:12 arniml
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-- added hierarchy t8039_notri
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-- added hierarchy t8039_notri
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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