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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- T8048 Microcontroller System
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-- T8048 Microcontroller System
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-- 8048 toplevel without tri-states
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-- 8048 toplevel without tri-states
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--
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--
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-- $Id: t8048_notri.vhd,v 1.2 2004-12-01 23:08:08 arniml Exp $
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-- $Id: t8048_notri.vhd,v 1.3 2004-12-02 22:08:42 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity t8048_notri is
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entity t8048_notri is
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generic (
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gate_port_input_g : integer := 1
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);
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port (
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port (
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xtal_i : in std_logic;
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xtal_i : in std_logic;
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reset_n_i : in std_logic;
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reset_n_i : in std_logic;
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t0_i : in std_logic;
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t0_i : in std_logic;
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t0_o : out std_logic;
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t0_o : out std_logic;
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Line 101... |
signal pmem_addr_s : std_logic_vector(11 downto 0);
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signal pmem_addr_s : std_logic_vector(11 downto 0);
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signal pmem_data_s : std_logic_vector( 7 downto 0);
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signal pmem_data_s : std_logic_vector( 7 downto 0);
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signal ea_s : std_logic;
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signal ea_s : std_logic;
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signal p1_in_s,
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p1_out_s : std_logic_vector( 7 downto 0);
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signal p2_in_s,
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p2_out_s : std_logic_vector( 7 downto 0);
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begin
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begin
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-----------------------------------------------------------------------------
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-- Check generics for valid values.
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-----------------------------------------------------------------------------
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-- pragma translate_off
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assert gate_port_input_g = 0 or gate_port_input_g = 1
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report "gate_port_input_g must be either 1 or 0!"
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severity failure;
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-- pragma translate_on
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t48_core_b : t48_core
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t48_core_b : t48_core
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generic map (
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generic map (
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xtal_div_3_g => 1,
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xtal_div_3_g => 1,
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register_mnemonic_g => 1,
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register_mnemonic_g => 1,
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include_port1_g => 1,
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include_port1_g => 1,
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Line 144... |
ale_o => ale_o,
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ale_o => ale_o,
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db_i => db_i,
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db_i => db_i,
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db_o => db_o,
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db_o => db_o,
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db_dir_o => db_dir_o,
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db_dir_o => db_dir_o,
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t1_i => t1_i,
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t1_i => t1_i,
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p2_i => p2_i,
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p2_i => p2_in_s,
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p2_o => p2_o,
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p2_o => p2_out_s,
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p2_low_imp_o => p2_low_imp_o,
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p2_low_imp_o => p2_low_imp_o,
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p1_i => p1_i,
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p1_i => p1_in_s,
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p1_o => p1_o,
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p1_o => p1_out_s,
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p1_low_imp_o => p1_low_imp_o,
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p1_low_imp_o => p1_low_imp_o,
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prog_n_o => prog_n_o,
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prog_n_o => prog_n_o,
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clk_i => xtal_i,
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clk_i => xtal_i,
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en_clk_i => xtal3_s,
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en_clk_i => xtal3_s,
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xtal3_o => xtal3_s,
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xtal3_o => xtal3_s,
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Line 164... |
pmem_data_i => pmem_data_s
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pmem_data_i => pmem_data_s
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Gate port 1 and 2 input bus with respetive output value
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-----------------------------------------------------------------------------
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gate_ports: if gate_port_input_g = 1 generate
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p1_in_s <= p1_i and p1_out_s;
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p2_in_s <= p2_i and p2_out_s;
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end generate;
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pass_ports: if gate_port_input_g = 0 generate
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p1_in_s <= p1_i;
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p2_in_s <= p2_i;
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end generate;
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p1_o <= p1_out_s;
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p2_o <= p2_out_s;
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-----------------------------------------------------------------------------
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-- Process ea
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-- Process ea
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--
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--
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-- Purpose:
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-- Purpose:
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-- Detects access to external program memory.
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-- Detects access to external program memory.
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-- Either by ea_i = '1' or when program memory address leaves address
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-- Either by ea_i = '1' or when program memory address leaves address
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/12/01 23:08:08 arniml
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-- update
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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