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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [wb_master.vhd] - Diff between revs 166 and 167

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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- The Wishbone master module.
-- The Wishbone master module.
--
--
-- $Id: wb_master.vhd,v 1.2 2005-05-06 18:54:03 arniml Exp $
-- $Id: wb_master.vhd,v 1.3 2005-05-08 10:36:07 arniml Exp $
--
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved
-- All rights reserved
--
--
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-- you have the latest version of this file.
-- you have the latest version of this file.
--
--
-- The latest version of this file can be found at:
-- The latest version of this file can be found at:
--      http://www.opencores.org/cvsweb.shtml/t48/
--      http://www.opencores.org/cvsweb.shtml/t48/
--
--
 
--
 
-- Short description:
 
--   This design implements a simple Wishbone bus master. It connects to the
 
--   BUS interface of the T48 uController core.
 
--
 
--   The CPU clock is suppressed with en_clk_o to stall the CPU until the
 
--   acknowledge signal from the peripheral is detected.
 
--
 
--   The adr_i input selects between configuration and Wishbone address range:
 
--     1 - configuration range
 
--     0 - Wishbone range
 
--
 
--   When configuration range is selected, two address register are accessible.
 
--     000h -> adr1
 
--     001h -> adr2
 
--   These registers can be read and written with movx to their addresses.
 
--
 
--   When Wishbone range is selected, all movx generate Wishbone bus cycles
 
--   (either read or write) at following address:
 
--     Wishbone address = adr2 & adr1 & address of movx
 
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 
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    en_clk_o    : out std_logic;
    en_clk_o    : out std_logic;
    -- T48 Interface ----------------------------------------------------------
    -- T48 Interface ----------------------------------------------------------
    ale_i       : in  std_logic;
    ale_i       : in  std_logic;
    rd_n_i      : in  std_logic;
    rd_n_i      : in  std_logic;
    wr_n_i      : in  std_logic;
    wr_n_i      : in  std_logic;
    sel_range_i : in  std_logic_vector( 1 downto 0);
    adr_i    : in  std_logic;
    db_bus_i    : in  std_logic_vector( 7 downto 0);
    db_bus_i    : in  std_logic_vector( 7 downto 0);
    db_bus_o    : out std_logic_vector( 7 downto 0);
    db_bus_o    : out std_logic_vector( 7 downto 0);
    -- Wishbone Interface -----------------------------------------------------
    -- Wishbone Interface -----------------------------------------------------
    wb_cyc_o    : out std_logic;
    wb_cyc_o    : out std_logic;
    wb_stb_o    : out std_logic;
    wb_stb_o    : out std_logic;
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begin
begin
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Select signal generation
  -- Select signal generation
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  sel_adr1_s <= sel_range_i = "01";
  sel_adr1_s <= adr_i = '1' and adr_q(word_t'range) = "00000000";
  sel_adr2_s <= sel_range_i = "10";
  sel_adr2_s <= adr_i = '1' and adr_q(word_t'range) = "00000001";
  sel_wb_s   <= sel_range_i = "00";
  sel_wb_s   <= adr_i = '0';
 
 
  wr_s       <= wr_n_i = '0';
  wr_s       <= wr_n_i = '0';
  rd_s       <= rd_n_i = '0';
  rd_s       <= rd_n_i = '0';
 
 
 
 
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    wb_stb_o <= '0';
    wb_stb_o <= '0';
    en_clk_o <= '1';
    en_clk_o <= '1';
    state_s  <= IDLE;
    state_s  <= IDLE;
 
 
    case state_q is
    case state_q is
 
      -- Idle State: Wait for read or write access ----------------------------
      when IDLE =>
      when IDLE =>
        if sel_wb_s and (wr_s or rd_s) then
        if sel_wb_s and (wr_s or rd_s) then
          state_s <= CYC;
          state_s <= CYC;
        end if;
        end if;
 
 
 
      -- WB Cycle State: Start Wishbone cycle and wait for ack ----------------
      when CYC =>
      when CYC =>
        wb_cyc_o <= '1';
        wb_cyc_o <= '1';
        wb_stb_o <= '1';
        wb_stb_o <= '1';
        en_clk_o <= '0';
        en_clk_o <= '0';
 
 
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          state_s <= WAIT_INACT;
          state_s <= WAIT_INACT;
        else
        else
          state_s <= CYC;
          state_s <= CYC;
        end if;
        end if;
 
 
 
      -- Wait inact State: Wait for end of T48 access -------------------------
      when WAIT_INACT =>
      when WAIT_INACT =>
        if not wr_s and not rd_s then
        if not wr_s and not rd_s then
          state_s <= IDLE;
          state_s <= IDLE;
        else
        else
          state_s <= WAIT_INACT;
          state_s <= WAIT_INACT;
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  --  Output multiplexer
  --  Output multiplexer
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  db_bus_o <=   adr_q(word_t'length*2 - 1 downto word_t'length)
  db_bus_o <=   adr_q(word_t'length*2 - 1 downto word_t'length)
              when sel_adr1_s else
              when sel_adr1_s else
                adr_q(word_t'length*3 - 1 downto word_t'length*2)
                adr_q(word_t'length*3 - 1 downto word_t'length*2)
              when sel_adr1_s else
              when sel_adr2_s else
                wb_dat_i;
                wb_dat_i;
 
 
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Output mapping
  -- Output mapping
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.2  2005/05/06 18:54:03  arniml
 
-- assign default for state_s
 
--
-- Revision 1.1  2005/05/05 19:49:03  arniml
-- Revision 1.1  2005/05/05 19:49:03  arniml
-- initial check-in
-- initial check-in
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
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