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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Wishbone master module.
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-- The Wishbone master module.
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--
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--
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-- $Id: wb_master.vhd,v 1.2 2005-05-06 18:54:03 arniml Exp $
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-- $Id: wb_master.vhd,v 1.3 2005-05-08 10:36:07 arniml Exp $
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--
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--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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--
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--
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-- Short description:
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-- This design implements a simple Wishbone bus master. It connects to the
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-- BUS interface of the T48 uController core.
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--
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-- The CPU clock is suppressed with en_clk_o to stall the CPU until the
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-- acknowledge signal from the peripheral is detected.
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--
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-- The adr_i input selects between configuration and Wishbone address range:
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-- 1 - configuration range
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-- 0 - Wishbone range
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--
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-- When configuration range is selected, two address register are accessible.
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-- 000h -> adr1
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-- 001h -> adr2
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-- These registers can be read and written with movx to their addresses.
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--
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-- When Wishbone range is selected, all movx generate Wishbone bus cycles
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-- (either read or write) at following address:
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-- Wishbone address = adr2 & adr1 & address of movx
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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en_clk_o : out std_logic;
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en_clk_o : out std_logic;
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-- T48 Interface ----------------------------------------------------------
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-- T48 Interface ----------------------------------------------------------
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ale_i : in std_logic;
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ale_i : in std_logic;
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rd_n_i : in std_logic;
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rd_n_i : in std_logic;
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wr_n_i : in std_logic;
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wr_n_i : in std_logic;
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sel_range_i : in std_logic_vector( 1 downto 0);
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adr_i : in std_logic;
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db_bus_i : in std_logic_vector( 7 downto 0);
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db_bus_i : in std_logic_vector( 7 downto 0);
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db_bus_o : out std_logic_vector( 7 downto 0);
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db_bus_o : out std_logic_vector( 7 downto 0);
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-- Wishbone Interface -----------------------------------------------------
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-- Wishbone Interface -----------------------------------------------------
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wb_cyc_o : out std_logic;
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wb_cyc_o : out std_logic;
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wb_stb_o : out std_logic;
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wb_stb_o : out std_logic;
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Select signal generation
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-- Select signal generation
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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sel_adr1_s <= sel_range_i = "01";
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sel_adr1_s <= adr_i = '1' and adr_q(word_t'range) = "00000000";
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sel_adr2_s <= sel_range_i = "10";
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sel_adr2_s <= adr_i = '1' and adr_q(word_t'range) = "00000001";
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sel_wb_s <= sel_range_i = "00";
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sel_wb_s <= adr_i = '0';
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wr_s <= wr_n_i = '0';
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wr_s <= wr_n_i = '0';
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rd_s <= rd_n_i = '0';
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rd_s <= rd_n_i = '0';
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wb_stb_o <= '0';
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wb_stb_o <= '0';
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en_clk_o <= '1';
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en_clk_o <= '1';
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state_s <= IDLE;
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state_s <= IDLE;
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case state_q is
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case state_q is
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-- Idle State: Wait for read or write access ----------------------------
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when IDLE =>
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when IDLE =>
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if sel_wb_s and (wr_s or rd_s) then
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if sel_wb_s and (wr_s or rd_s) then
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state_s <= CYC;
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state_s <= CYC;
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end if;
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end if;
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-- WB Cycle State: Start Wishbone cycle and wait for ack ----------------
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when CYC =>
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when CYC =>
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wb_cyc_o <= '1';
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wb_cyc_o <= '1';
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wb_stb_o <= '1';
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wb_stb_o <= '1';
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en_clk_o <= '0';
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en_clk_o <= '0';
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state_s <= WAIT_INACT;
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state_s <= WAIT_INACT;
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else
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else
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state_s <= CYC;
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state_s <= CYC;
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end if;
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end if;
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-- Wait inact State: Wait for end of T48 access -------------------------
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when WAIT_INACT =>
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when WAIT_INACT =>
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if not wr_s and not rd_s then
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if not wr_s and not rd_s then
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state_s <= IDLE;
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state_s <= IDLE;
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else
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else
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state_s <= WAIT_INACT;
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state_s <= WAIT_INACT;
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-- Output multiplexer
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-- Output multiplexer
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length)
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db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length)
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when sel_adr1_s else
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when sel_adr1_s else
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adr_q(word_t'length*3 - 1 downto word_t'length*2)
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adr_q(word_t'length*3 - 1 downto word_t'length*2)
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when sel_adr1_s else
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when sel_adr2_s else
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wb_dat_i;
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wb_dat_i;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-- Output mapping
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2005/05/06 18:54:03 arniml
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-- assign default for state_s
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--
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-- Revision 1.1 2005/05/05 19:49:03 arniml
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-- Revision 1.1 2005/05/05 19:49:03 arniml
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-- initial check-in
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-- initial check-in
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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