| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Wishbone master module.
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-- The Wishbone master module.
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--
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--
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-- $Id: wb_master.vhd,v 1.3 2005-05-08 10:36:07 arniml Exp $
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-- $Id: wb_master.vhd,v 1.4 2005-05-10 22:36:23 arniml Exp $
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--
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--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 113... |
Line 113... |
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signal wr_s,
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signal wr_s,
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rd_s : boolean;
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rd_s : boolean;
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signal adr_q : std_logic_vector(23 downto 0);
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signal adr_q : std_logic_vector(23 downto 0);
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signal wb_dat_q : std_logic_vector( 7 downto 0);
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Select signal generation
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-- Select signal generation
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| Line 137... |
Line 138... |
--
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--
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seq: process (res_i, xtal_i)
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seq: process (res_i, xtal_i)
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begin
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begin
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if res_i = res_active_c then
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if res_i = res_active_c then
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adr_q <= (others => '0');
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adr_q <= (others => '0');
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wb_dat_q <= (others => '0');
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state_q <= IDLE;
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state_q <= IDLE;
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elsif xtal_i'event and xtal_i = clk_active_c then
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elsif xtal_i'event and xtal_i = clk_active_c then
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-- Address register -----------------------------------------------------
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-- Address register -----------------------------------------------------
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-- update lowest address byte
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-- update lowest address byte
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| Line 154... |
Line 156... |
-- set adr2 part
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-- set adr2 part
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if wr_s and sel_adr2_s then
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if wr_s and sel_adr2_s then
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adr_q(word_t'length*3 - 1 downto word_t'length*2) <= db_bus_i;
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adr_q(word_t'length*3 - 1 downto word_t'length*2) <= db_bus_i;
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end if;
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end if;
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-- Data from peripheral has to be saved ---------------------------------
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if wb_ack_i = '1' then
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wb_dat_q <= wb_dat_i;
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end if;
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-- FSM state ------------------------------------------------------------
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-- FSM state ------------------------------------------------------------
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state_q <= state_s;
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state_q <= state_s;
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end if;
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end if;
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end process seq;
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end process seq;
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| Line 225... |
Line 232... |
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length)
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db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length)
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when sel_adr1_s else
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when sel_adr1_s else
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adr_q(word_t'length*3 - 1 downto word_t'length*2)
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adr_q(word_t'length*3 - 1 downto word_t'length*2)
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when sel_adr2_s else
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when sel_adr2_s else
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wb_dat_i;
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wb_dat_q;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-- Output mapping
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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wb_adr_o <= adr_q;
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wb_adr_o <= adr_q;
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wb_dat_o <= db_bus_i;
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wb_dat_o <= db_bus_i;
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wb_we_o <= '1'
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wb_we_o <= '1'
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when wr_s else
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when wr_s and sel_wb_s else
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'0';
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'0';
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end rtl;
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end rtl;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2005/05/08 10:36:07 arniml
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-- simplify address range:
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-- - configuration range
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-- - Wishbone range
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--
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-- Revision 1.2 2005/05/06 18:54:03 arniml
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-- Revision 1.2 2005/05/06 18:54:03 arniml
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-- assign default for state_s
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-- assign default for state_s
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--
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--
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-- Revision 1.1 2005/05/05 19:49:03 arniml
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-- Revision 1.1 2005/05/05 19:49:03 arniml
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-- initial check-in
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-- initial check-in
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