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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Wishbone master module.
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-- The Wishbone master module.
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--
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--
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-- $Id: wb_master.vhd,v 1.4 2005-05-10 22:36:23 arniml Exp $
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-- $Id: wb_master.vhd,v 1.5 2005-06-11 10:16:05 arniml Exp $
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--
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--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.t48_pack.all;
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use work.t48_pack.all;
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entity wb_master is
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entity t48_wb_master is
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port (
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port (
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xtal_i : in std_logic;
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xtal_i : in std_logic;
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res_i : in std_logic;
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res_i : in std_logic;
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en_clk_o : out std_logic;
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en_clk_o : out std_logic;
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wb_ack_i : in std_logic;
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wb_ack_i : in std_logic;
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wb_dat_i : in std_logic_vector( 7 downto 0);
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wb_dat_i : in std_logic_vector( 7 downto 0);
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wb_dat_o : out std_logic_vector( 7 downto 0)
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wb_dat_o : out std_logic_vector( 7 downto 0)
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);
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);
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end wb_master;
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end t48_wb_master;
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architecture rtl of wb_master is
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architecture rtl of t48_wb_master is
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|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Controller FSM
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-- Controller FSM
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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type state_t is (IDLE, CYC, WAIT_INACT);
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type state_t is (IDLE, CYC, WAIT_INACT);
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2005/05/10 22:36:23 arniml
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-- save data from wishbone bus in register bank with wb_ack
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-- necessary to hold data from peripheral/memory until it is read by T48
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--
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-- Revision 1.3 2005/05/08 10:36:07 arniml
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-- Revision 1.3 2005/05/08 10:36:07 arniml
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-- simplify address range:
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-- simplify address range:
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-- - configuration range
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-- - configuration range
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-- - Wishbone range
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-- - Wishbone range
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--
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--
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