| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- T48 Microcontroller Core
|
-- T48 Microcontroller Core
|
--
|
--
|
-- $Id: t48_core.vhd,v 1.8 2005-05-04 20:12:37 arniml Exp $
|
-- $Id: t48_core.vhd,v 1.9 2005-06-11 10:08:43 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
| Line 117... |
Line 117... |
);
|
);
|
|
|
end t48_core;
|
end t48_core;
|
|
|
|
|
use work.alu_pack.alu_op_t;
|
use work.t48_alu_pack.alu_op_t;
|
use work.cond_branch_pack.branch_conditions_t;
|
use work.t48_cond_branch_pack.branch_conditions_t;
|
use work.cond_branch_pack.comp_value_t;
|
use work.t48_cond_branch_pack.comp_value_t;
|
use work.dmem_ctrl_pack.dmem_addr_ident_t;
|
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
|
use work.pmem_ctrl_pack.pmem_addr_ident_t;
|
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;
|
use work.t48_comp_pack.all;
|
use work.t48_comp_pack.all;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.word_t;
|
use work.t48_pack.word_t;
|
use work.t48_pack.pmem_addr_t;
|
use work.t48_pack.pmem_addr_t;
|
use work.t48_pack.mstate_t;
|
use work.t48_pack.mstate_t;
|
| Line 274... |
Line 274... |
-- pragma translate_on
|
-- pragma translate_on
|
|
|
|
|
en_clk_s <= to_boolean(en_clk_i);
|
en_clk_s <= to_boolean(en_clk_i);
|
|
|
alu_b : alu
|
alu_b : t48_alu
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
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en_clk_i => en_clk_s,
|
data_i => t48_data_s,
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data_i => t48_data_s,
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| Line 297... |
Line 297... |
accu_low_i => alu_accu_low_s,
|
accu_low_i => alu_accu_low_s,
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p06_temp_reg_i => alu_p06_temp_reg_s,
|
p06_temp_reg_i => alu_p06_temp_reg_s,
|
p60_temp_reg_i => alu_p60_temp_reg_s
|
p60_temp_reg_i => alu_p60_temp_reg_s
|
);
|
);
|
|
|
bus_mux_b : bus_mux
|
bus_mux_b : t48_bus_mux
|
port map (
|
port map (
|
alu_data_i => alu_data_s,
|
alu_data_i => alu_data_s,
|
bus_data_i => bus_data_s,
|
bus_data_i => bus_data_s,
|
dec_data_i => dec_data_s,
|
dec_data_i => dec_data_s,
|
dm_data_i => dm_data_s,
|
dm_data_i => dm_data_s,
|
| Line 311... |
Line 311... |
psw_data_i => psw_data_s,
|
psw_data_i => psw_data_s,
|
tim_data_i => tim_data_s,
|
tim_data_i => tim_data_s,
|
data_o => t48_data_s
|
data_o => t48_data_s
|
);
|
);
|
|
|
clock_ctrl_b : clock_ctrl
|
clock_ctrl_b : t48_clock_ctrl
|
generic map (
|
generic map (
|
xtal_div_3_g => xtal_div_3_g
|
xtal_div_3_g => xtal_div_3_g
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
| Line 336... |
Line 336... |
prog_o => prog_s,
|
prog_o => prog_s,
|
rd_o => rd_s,
|
rd_o => rd_s,
|
wr_o => wr_s
|
wr_o => wr_s
|
);
|
);
|
|
|
cond_branch_b : cond_branch
|
cond_branch_b : t48_cond_branch
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
|
en_clk_i => en_clk_s,
|
compute_take_i => cnd_compute_take_s,
|
compute_take_i => cnd_compute_take_s,
|
| Line 356... |
Line 356... |
carry_i => psw_carry_s,
|
carry_i => psw_carry_s,
|
comp_value_i => cnd_comp_value_s
|
comp_value_i => cnd_comp_value_s
|
);
|
);
|
|
|
use_db_bus: if include_bus_g = 1 generate
|
use_db_bus: if include_bus_g = 1 generate
|
db_bus_b : db_bus
|
db_bus_b : t48_db_bus
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
|
en_clk_i => en_clk_s,
|
ea_i => ea_i,
|
ea_i => ea_i,
|
| Line 381... |
Line 381... |
bus_data_s <= (others => bus_idle_level_c);
|
bus_data_s <= (others => bus_idle_level_c);
|
db_o <= (others => '0');
|
db_o <= (others => '0');
|
db_dir_o <= '0';
|
db_dir_o <= '0';
|
end generate;
|
end generate;
|
|
|
decoder_b : decoder
|
decoder_b : t48_decoder
|
generic map (
|
generic map (
|
register_mnemonic_g => register_mnemonic_g
|
register_mnemonic_g => register_mnemonic_g
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
| Line 468... |
Line 468... |
psw_write_f0_o => psw_write_f0_s,
|
psw_write_f0_o => psw_write_f0_s,
|
psw_write_bs_o => psw_write_bs_s,
|
psw_write_bs_o => psw_write_bs_s,
|
tim_overflow_i => tim_overflow_s
|
tim_overflow_i => tim_overflow_s
|
);
|
);
|
|
|
dmem_ctrl_b : dmem_ctrl
|
dmem_ctrl_b : t48_dmem_ctrl
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
|
en_clk_i => en_clk_s,
|
data_i => t48_data_s,
|
data_i => t48_data_s,
|
| Line 487... |
Line 487... |
dmem_we_o => dmem_we_o,
|
dmem_we_o => dmem_we_o,
|
dmem_data_o => dmem_data_o
|
dmem_data_o => dmem_data_o
|
);
|
);
|
|
|
use_timer: if include_timer_g = 1 generate
|
use_timer: if include_timer_g = 1 generate
|
timer_b : timer
|
timer_b : t48_timer
|
generic map (
|
generic map (
|
sample_t1_state_g => sample_t1_state_g
|
sample_t1_state_g => sample_t1_state_g
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
| Line 516... |
Line 516... |
end generate;
|
end generate;
|
|
|
tim_overflow_s <= to_boolean(tim_of_s);
|
tim_overflow_s <= to_boolean(tim_of_s);
|
|
|
use_p1: if include_port1_g = 1 generate
|
use_p1: if include_port1_g = 1 generate
|
p1_b : p1
|
p1_b : t48_p1
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
|
en_clk_i => en_clk_s,
|
data_i => t48_data_s,
|
data_i => t48_data_s,
|
| Line 539... |
Line 539... |
p1_o <= (others => '0');
|
p1_o <= (others => '0');
|
p1_low_imp_o <= '0';
|
p1_low_imp_o <= '0';
|
end generate;
|
end generate;
|
|
|
use_p2: if include_port2_g = 1 generate
|
use_p2: if include_port2_g = 1 generate
|
p2_b : p2
|
p2_b : t48_p2
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
|
en_clk_i => en_clk_s,
|
data_i => t48_data_s,
|
data_i => t48_data_s,
|
| Line 566... |
Line 566... |
p2_data_s <= (others => bus_idle_level_c);
|
p2_data_s <= (others => bus_idle_level_c);
|
p2_o <= (others => '0');
|
p2_o <= (others => '0');
|
p2_low_imp_o <= '0';
|
p2_low_imp_o <= '0';
|
end generate;
|
end generate;
|
|
|
pmem_ctrl_b : pmem_ctrl
|
pmem_ctrl_b : t48_pmem_ctrl
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
|
en_clk_i => en_clk_s,
|
data_i => t48_data_s,
|
data_i => t48_data_s,
|
| Line 585... |
Line 585... |
read_pmem_i => pm_read_pmem_s,
|
read_pmem_i => pm_read_pmem_s,
|
pmem_addr_o => pmem_addr_s,
|
pmem_addr_o => pmem_addr_s,
|
pmem_data_i => pmem_data_i
|
pmem_data_i => pmem_data_i
|
);
|
);
|
|
|
psw_b : psw
|
psw_b : t48_psw
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
res_i => reset_i,
|
res_i => reset_i,
|
en_clk_i => en_clk_s,
|
en_clk_i => en_clk_s,
|
data_i => t48_data_s,
|
data_i => t48_data_s,
|
| Line 629... |
Line 629... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.8 2005/05/04 20:12:37 arniml
|
|
-- Fix bug report:
|
|
-- "Wrong clock applied to T0"
|
|
-- t0_o is generated inside clock_ctrl with a separate flip-flop running
|
|
-- with xtal_i
|
|
--
|
-- Revision 1.7 2004/05/01 11:58:04 arniml
|
-- Revision 1.7 2004/05/01 11:58:04 arniml
|
-- update notice about expander port instructions
|
-- update notice about expander port instructions
|
--
|
--
|
-- Revision 1.6 2004/04/07 22:09:03 arniml
|
-- Revision 1.6 2004/04/07 22:09:03 arniml
|
-- remove unused signals
|
-- remove unused signals
|
