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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- T48 Microcontroller Core
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-- T48 Microcontroller Core
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--
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--
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-- $Id: t48_core.vhd,v 1.10 2005-11-01 21:32:58 arniml Exp $
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-- $Id: t48_core.vhd,v 1.11 2006-06-20 00:46:04 arniml Exp $
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--
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--
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-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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);
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);
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port (
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port (
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-- T48 Interface ----------------------------------------------------------
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-- T48 Interface ----------------------------------------------------------
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xtal_i : in std_logic;
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xtal_i : in std_logic;
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xtal_en_i : in std_logic;
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reset_i : in std_logic;
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reset_i : in std_logic;
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t0_i : in std_logic;
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t0_i : in std_logic;
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t0_o : out std_logic;
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t0_o : out std_logic;
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t0_dir_o : out std_logic;
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t0_dir_o : out std_logic;
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int_n_i : in std_logic;
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int_n_i : in std_logic;
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architecture struct of t48_core is
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architecture struct of t48_core is
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signal t48_data_s : word_t;
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signal t48_data_s : word_t;
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signal xtal_en_s : boolean;
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signal en_clk_s : boolean;
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signal en_clk_s : boolean;
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-- ALU signals
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-- ALU signals
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signal alu_data_s : word_t;
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signal alu_data_s : word_t;
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signal alu_write_accu_s : boolean;
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signal alu_write_accu_s : boolean;
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report "include_bus_g must be either 1 or 0!"
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report "include_bus_g must be either 1 or 0!"
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severity failure;
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severity failure;
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-- pragma translate_on
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-- pragma translate_on
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xtal_en_s <= to_boolean(xtal_en_i);
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en_clk_s <= to_boolean(en_clk_i);
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en_clk_s <= to_boolean(en_clk_i);
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alu_b : t48_alu
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alu_b : t48_alu
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port map (
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port map (
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clk_i => clk_i,
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clk_i => clk_i,
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xtal_div_3_g => xtal_div_3_g
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xtal_div_3_g => xtal_div_3_g
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)
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)
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port map (
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port map (
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clk_i => clk_i,
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clk_i => clk_i,
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xtal_i => xtal_i,
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xtal_i => xtal_i,
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xtal_en_i => xtal_en_s,
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res_i => reset_i,
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res_i => reset_i,
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en_clk_i => en_clk_s,
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en_clk_i => en_clk_s,
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xtal3_o => xtal3_s,
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xtal3_o => xtal3_s,
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t0_o => t0_o,
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t0_o => t0_o,
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multi_cycle_i => clk_multi_cycle_s,
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multi_cycle_i => clk_multi_cycle_s,
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port map (
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port map (
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clk_i => clk_i,
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clk_i => clk_i,
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res_i => reset_i,
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res_i => reset_i,
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en_clk_i => en_clk_s,
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en_clk_i => en_clk_s,
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xtal_i => xtal_i,
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xtal_i => xtal_i,
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xtal_en_i => xtal_en_s,
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ea_i => ea_i,
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ea_i => ea_i,
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ale_i => ale_s,
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ale_i => ale_s,
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int_n_i => int_n_i,
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int_n_i => int_n_i,
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t0_dir_o => t0_dir_o,
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t0_dir_o => t0_dir_o,
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data_i => t48_data_s,
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data_i => t48_data_s,
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port map (
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port map (
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clk_i => clk_i,
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clk_i => clk_i,
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res_i => reset_i,
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res_i => reset_i,
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en_clk_i => en_clk_s,
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en_clk_i => en_clk_s,
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xtal_i => xtal_i,
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xtal_i => xtal_i,
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xtal_en_i => xtal_en_s,
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data_i => t48_data_s,
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data_i => t48_data_s,
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data_o => p2_data_s,
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data_o => p2_data_s,
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write_p2_i => p2_write_p2_s,
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write_p2_i => p2_write_p2_s,
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write_exp_i => p2_write_exp_s,
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write_exp_i => p2_write_exp_s,
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read_p2_i => p2_read_p2_s,
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read_p2_i => p2_read_p2_s,
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.10 2005/11/01 21:32:58 arniml
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-- wire signals for P2 low impeddance marker issue
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--
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-- Revision 1.9 2005/06/11 10:08:43 arniml
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-- Revision 1.9 2005/06/11 10:08:43 arniml
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-- introduce prefix 't48_' for all packages, entities and configurations
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-- introduce prefix 't48_' for all packages, entities and configurations
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--
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--
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-- Revision 1.8 2005/05/04 20:12:37 arniml
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-- Revision 1.8 2005/05/04 20:12:37 arniml
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-- Fix bug report:
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-- Fix bug report:
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