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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- $Id: t48_core_comp_pack-p.vhd,v 1.4 2006-06-20 00:46:04 arniml Exp $
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-- $Id: t48_core_comp_pack-p.vhd,v 1.5 2006-06-21 01:03:28 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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pmem_addr_o : out std_logic_vector(11 downto 0);
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pmem_addr_o : out std_logic_vector(11 downto 0);
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pmem_data_i : in std_logic_vector( 7 downto 0)
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pmem_data_i : in std_logic_vector( 7 downto 0)
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);
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);
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end component;
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end component;
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component syn_rom
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component generic_ram_ena
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generic (
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generic (
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address_width_g : positive := 10
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addr_width_g : integer := 10;
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data_width_g : integer := 8
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);
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);
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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rom_addr_i : in std_logic_vector(address_width_g-1 downto 0);
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a_i : in std_logic_vector(addr_width_g-1 downto 0);
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rom_data_o : out std_logic_vector(7 downto 0)
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we_i : in std_logic;
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ena_i : in std_logic;
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d_i : in std_logic_vector(data_width_g-1 downto 0);
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d_o : out std_logic_vector(data_width_g-1 downto 0)
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);
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);
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end component;
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end component;
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component syn_ram
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component t48_rom
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generic (
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port (
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address_width_g : positive := 8
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clk_i : in std_logic;
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rom_addr_i : in std_logic_vector(9 downto 0);
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rom_data_o : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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component t49_rom
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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res_i : in std_logic;
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rom_addr_i : in std_logic_vector(10 downto 0);
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ram_addr_i : in std_logic_vector(address_width_g-1 downto 0);
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rom_data_o : out std_logic_vector( 7 downto 0)
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ram_data_i : in std_logic_vector(7 downto 0);
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ram_we_i : in std_logic;
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ram_data_o : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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end t48_core_comp_pack;
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end t48_core_comp_pack;
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