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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The testbench for t8039.
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-- The testbench for t8039.
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--
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--
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-- $Id: tb_t8039.vhd,v 1.3 2006-06-21 01:04:05 arniml Exp $
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-- $Id: tb_t8039.vhd,v 1.4 2006-06-22 00:21:58 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 84... |
Line 84... |
signal res_n_s : std_logic;
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signal res_n_s : std_logic;
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signal int_n_s : std_logic;
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signal int_n_s : std_logic;
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signal ale_s : std_logic;
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signal ale_s : std_logic;
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signal psen_n_s : std_logic;
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signal psen_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal rom_addr_s : std_logic_vector(11 downto 0);
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signal rom_data_s : std_logic_vector( 7 downto 0);
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signal ram_data_to_s : std_logic_vector( 7 downto 0);
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signal ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ram_addr_s : std_logic_vector( 7 downto 0);
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signal ram_we_s : std_logic;
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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Line 186... |
p2_b,
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p2_b,
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db_b)
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db_b)
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begin
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begin
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ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
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ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
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if ale_s = '1' then
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if ale_s'event and ale_s = '0' then
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if not is_X(db_b) then
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if not is_X(db_b) then
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ext_mem_addr_s(7 downto 0) <= db_b;
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ext_mem_addr_s(7 downto 0) <= db_b;
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else
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else
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ext_mem_addr_s(7 downto 0) <= (others => '0');
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ext_mem_addr_s(7 downto 0) <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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if wr_n_s'event and wr_n_s = '1' then
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if wr_n_s'event and wr_n_s = '1' then
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ext_ram_we_s <= '0';
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end if;
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if wr_n_s'event and wr_n_s = '0' then
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ext_ram_we_s <= '1';
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ext_ram_we_s <= '1';
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end if;
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end if;
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-- if clk_s'event then
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-- ext_ram_we_s <= '0';
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-- end if;
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end process ext_mem;
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end process ext_mem;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 299... |
Line 292... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2006/06/21 01:04:05 arniml
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-- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom
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--
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-- Revision 1.2 2005/11/01 21:22:28 arniml
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-- Revision 1.2 2005/11/01 21:22:28 arniml
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-- fix address assignment
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-- fix address assignment
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--
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--
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-- Revision 1.1 2004/04/18 19:00:07 arniml
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-- Revision 1.1 2004/04/18 19:00:07 arniml
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-- initial check-in
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-- initial check-in
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