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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Clock Control unit.
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-- The Clock Control unit.
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-- Clock States and Machine Cycles are generated here.
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-- Clock States and Machine Cycles are generated here.
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--
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--
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-- $Id: clock_ctrl.vhd,v 1.1 2004-03-23 21:31:52 arniml Exp $
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-- $Id: clock_ctrl.vhd,v 1.2 2004-03-28 12:55:06 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 228... |
Line 228... |
-- PSEN is set at the end of XTAL3
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-- PSEN is set at the end of XTAL3
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if assert_psen_i then
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if assert_psen_i then
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psen_q <= true;
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psen_q <= true;
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end if;
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end if;
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end if;
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-- PROG is set at the and of XTAL2
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-- PROG is set at the and of XTAL2
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if xtal2_s and multi_cycle_q and not second_cycle_q and
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if xtal2_s and multi_cycle_q and not second_cycle_q and
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assert_prog_i then
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assert_prog_i then
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prog_q <= true;
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prog_q <= true;
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end if;
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end if;
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end if;
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-- ALE is removed at the end of XTAL2 of every machine cycle
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-- ALE is removed at the end of XTAL2 of every machine cycle
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if xtal2_s then
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if xtal2_s then
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ale_q <= false;
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ale_q <= false;
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end if;
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end if;
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| Line 375... |
Line 375... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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