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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The testbench for t48_core.
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-- The testbench for t48_core.
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--
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--
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-- $Id: tb.vhd,v 1.3 2004-03-26 22:39:28 arniml Exp $
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-- $Id: tb.vhd,v 1.4 2004-03-28 21:30:25 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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signal t48_p1_s : std_logic_vector( 7 downto 0);
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signal t48_p1_s : std_logic_vector( 7 downto 0);
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signal p1_limp_s : std_logic;
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signal p1_limp_s : std_logic;
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signal p2_s : std_logic_vector( 7 downto 0);
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signal p2_s : std_logic_vector( 7 downto 0);
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signal t48_p2_s : std_logic_vector( 7 downto 0);
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signal t48_p2_s : std_logic_vector( 7 downto 0);
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signal p2_limp_s : std_logic;
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signal p2_limp_s : std_logic;
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signal prog_n_s : std_logic;
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signal bus_s : std_logic_vector( 7 downto 0);
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signal bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal bus_dir_s : std_logic;
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signal bus_dir_s : std_logic;
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p2_o => t48_p2_s,
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p2_o => t48_p2_s,
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p2_limp_o => p2_limp_s,
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p2_limp_o => p2_limp_s,
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p1_i => p1_s,
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p1_i => p1_s,
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p1_o => t48_p1_s,
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p1_o => t48_p1_s,
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p1_limp_o => p1_limp_s,
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p1_limp_o => p1_limp_s,
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prog_n_o => open,
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prog_n_o => prog_n_s,
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clk_i => xtal_s,
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clk_i => xtal_s,
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en_clk_i => xtal3_s,
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en_clk_i => xtal3_s,
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xtal3_o => xtal3_s,
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xtal3_o => xtal3_s,
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dmem_addr_o => ram_addr_s,
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dmem_addr_o => ram_addr_s,
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dmem_we_o => ram_we_s,
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dmem_we_o => ram_we_s,
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Line 343... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2004/03/26 22:39:28 arniml
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-- enhance simulation result string
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--
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-- Revision 1.2 2004/03/24 23:22:35 arniml
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-- Revision 1.2 2004/03/24 23:22:35 arniml
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-- put ext_ram on falling clock edge to sample the write enable properly
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-- put ext_ram on falling clock edge to sample the write enable properly
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--
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--
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-- Revision 1.1 2004/03/24 21:42:10 arniml
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-- Revision 1.1 2004/03/24 21:42:10 arniml
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-- initial check-in
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-- initial check-in
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