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Line 29... |
signal INT0 : std_logic := '0';
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signal INT0 : std_logic := '0';
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signal P0 : std_logic_vector(7 downto 0);
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signal P0 : std_logic_vector(7 downto 0);
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signal P1 : std_logic_vector(7 downto 0);
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signal P1 : std_logic_vector(7 downto 0);
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signal P2 : std_logic_vector(7 downto 0);
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signal P2 : std_logic_vector(7 downto 0);
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signal P3 : std_logic_vector(7 downto 0);
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signal P3 : std_logic_vector(7 downto 0);
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signal p3_out : std_logic_vector(7 downto 0);
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begin
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begin
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u0 : entity work.T8032
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u0 : entity work.T8032
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port map(
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port map(
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Line 45... |
STB_O => STB_O,
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STB_O => STB_O,
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WE_O => WE_O,
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WE_O => WE_O,
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ADR_O => ADR_O,
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ADR_O => ADR_O,
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DAT_I => DAT_I,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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DAT_O => DAT_O,
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P0 => P0,
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P0_in => P0,
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P1 => P1,
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P1_in => P1,
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P2 => P2,
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P2_in => P2,
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P3 => P3,
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P3_in => P3,
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P0_out => P0,
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P1_out => P1,
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P2_out => P2,
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P3_out => P3_out,
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INT0 => INT0,
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INT0 => INT0,
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INT1 => '1',
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INT1 => '1',
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T0 => '1',
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T0 => '1',
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T1 => '1',
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T1 => '1',
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T2 => '1',
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T2 => '1',
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Line 88... |
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DAT_I <= ROM_D when TAG0_O = '0' else RAM_D when ADR_O(15 downto 11) = "00000" else "11111111";
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DAT_I <= ROM_D when TAG0_O = '0' else RAM_D when ADR_O(15 downto 11) = "00000" else "11111111";
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ACK_I <= '1' when ADR_O_r = ADR_O else '0';
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ACK_I <= '1' when ADR_O_r = ADR_O else '0';
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P3(0) <= RXD;
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P3(0) <= RXD;
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P3(7 downto 1) <= P3_out(7 downto 1);
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process (CLK_I)
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process (CLK_I)
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begin
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begin
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if CLK_I'event and CLK_I = '1' then
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if CLK_I'event and CLK_I = '1' then
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ADR_O_r <= ADR_O;
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ADR_O_r <= ADR_O;
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end if;
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end if;
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end process;
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end process;
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as : AsyncStim
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as : AsyncStim
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generic map(FileName => "BASIC.txt", InterCharDelay => 5000 us, Baud => 115200, Bits => 8)
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generic map(FileName => "BASIC.txt", InterCharDelay => 5000 us, Baud => 57600, Bits => 8)
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port map(RXD);
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port map(RXD);
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al : AsyncLog
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al : AsyncLog
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generic map(FileName => "RX_Log.txt", Baud => 115200, Bits => 8)
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generic map(FileName => "RX_Log.txt", Baud => 57600, Bits => 8)
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port map(TXD);
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port map(TXD);
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CLK_I <= not CLK_I after 45 ns;
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CLK_I <= not CLK_I after 45 ns;
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RST_I <= '0' after 200 ns;
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RST_I <= '0' after 200 ns;
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