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Line 43... |
-- Limitations :
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-- Limitations :
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--
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--
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-- File history :
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-- File history :
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-- 0208 : Initial release
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-- 0208 : Initial release
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-- 0218 : Fixed data out at write
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-- 0218 : Fixed data out at write
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-- 0220 : Added support for XST
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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entity SSRAM is
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entity SSRAM is
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generic(
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generic(
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AddrWidth : integer := 16;
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AddrWidth : integer := 11;
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DataWidth : integer := 8
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DataWidth : integer := 8
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);
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);
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port(
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port(
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Clk : in std_logic;
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Clk : in std_logic;
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CE_n : in std_logic;
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CE_n : in std_logic;
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Line 69... |
architecture behaviour of SSRAM is
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architecture behaviour of SSRAM is
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type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
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type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
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signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
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signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
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signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
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signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
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signal B : std_logic_vector(AddrWidth - 1 downto 0);
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begin
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begin
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process (Clk)
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process (Clk)
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begin
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begin
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if Clk'event and Clk = '1' then
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if Clk'event and Clk = '1' then
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-- pragma translate_off
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if (CE_n nor WE_n) = '1' then
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if not is_x(A) then
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RAM(to_integer(unsigned(B))) <= DIn;
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-- pragma translate_on
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DOut <= RAM(to_integer(unsigned(A(AddrWidth - 1 downto 0))));
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-- pragma translate_off
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end if;
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-- pragma translate_on
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if CE_n = '0' and WE_n = '0' then
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RAM(to_integer(unsigned(A_r))) <= DIn;
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if A_r = A then
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DOut <= DIn;
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end if;
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end if;
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end if;
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A_r <= A;
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A_r <= A;
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B <= A;
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end if;
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end if;
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end process;
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end process;
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DOut <= RAM(to_integer(unsigned(A_r)))
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-- pragma translate_off
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when not is_x(A_r) else (others => '-')
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-- pragma translate_on
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;
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end;
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end;
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No newline at end of file
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No newline at end of file
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