| Line 40... |
Line 40... |
};
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};
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|
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compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
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compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
|
if (first_cycle) {
|
if (first_cycle) {
|
first_cycle = FALSE;
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first_cycle = FALSE;
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reg_x = alu_x;
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reg_x = 0;
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reg_y = alu_y;
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reg_y = 0;
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reg_status = alu_status;
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reg_status = 8'b00100010;
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reg_a = 0; // TODO: check this
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reg_a = 0; // TODO: check this
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reg_result = 0;
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reg_result = 0;
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}
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}
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else {
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else {
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out ("CYCLE ", count_cycles, " COMPARE:");
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out ("CYCLE ", count_cycles, " COMPARE:");
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print inst;
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print inst;
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|
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case inst.input_kind {
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case inst.input_kind {
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ENABLED_VALID: {
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ENABLED_VALID: {
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out("CYCLE ", count_cycles, ": executing and comparing");
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out("CYCLE ", count_cycles, ": executing and comparing");
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execute();
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execute();
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};
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};
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DISABLED_VALID: {
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DISABLED_VALID: {
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out("CYCLE ", count_cycles, ": just comparing");
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out("CYCLE ", count_cycles, ": just comparing");
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};
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};
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default: {
|
RESET: {
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dut_error("error at e code");
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return;
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};
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};
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};
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default: {
|
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dut_error("error at e code");
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};
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};
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// here i have already calculated. must compare!
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// here i have already calculated. must compare!
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if (reg_result != alu_result) {
|
|
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//if (count_cycles > 10) {
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if (reg_result != alu_result) {
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print inst;
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print inst;
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print me;
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print me;
|
print alu_result;
|
print alu_result;
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print alu_status;
|
print alu_status;
|
print alu_x;
|
print alu_x;
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print alu_y;
|
print alu_y;
|
|
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dut_error("WRONG!");
|
dut_error("WRONG!");
|
};
|
};
|
|
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if (reg_x != alu_x) {
|
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dut_error("WRONG!");
|
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};
|
|
|
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if (reg_y != alu_y) {
|
|
dut_error("WRONG!");
|
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};
|
|
|
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if (reg_status != alu_status) {
|
|
dut_error("WRONG!");
|
|
};
|
|
}
|
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};
|
|
|
|
execute() is {
|
|
case inst.alu_opcode {
|
|
ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
|
|
ADC_ZPG: { exec_sum(); };
|
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ADC_ZPX: { exec_sum(); };
|
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ADC_ABS: { exec_sum(); };
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ADC_ABX: { exec_sum(); };
|
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ADC_ABY: { exec_sum(); };
|
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ADC_IDX: { exec_sum(); };
|
|
ADC_IDY: { exec_sum(); };
|
|
|
|
AND_IMM: { exec_and(); }; // A,Z,N = A&M
|
|
AND_ZPG: { exec_and(); };
|
|
AND_ZPX: { exec_and(); };
|
|
AND_ABS: { exec_and(); };
|
|
AND_ABX: { exec_and(); };
|
|
AND_ABY: { exec_and(); };
|
|
AND_IDX: { exec_and(); };
|
|
AND_IDY: { exec_and(); };
|
|
|
|
ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
|
|
|
|
ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
|
|
ASL_ZPX: { exec_asl_mem(); };
|
|
ASL_ABS: { exec_asl_mem(); };
|
|
ASL_ABX: { exec_asl_mem(); };
|
|
|
|
default: {
|
|
//dut_error("unknown opcode");
|
|
}
|
|
};
|
|
};
|
|
|
|
exec_asl_acc() is {
|
|
reg_status[0:0] = reg_a[7:7];
|
|
reg_a = reg_a * 2;
|
|
update_z(reg_a);
|
|
update_n(reg_a);
|
|
reg_result = reg_a;
|
|
};
|
|
|
|
exec_asl_mem() is {
|
|
reg_status[0:0] = inst.alu_a[7:7];
|
|
reg_result = inst.alu_a * 2;
|
|
update_z(reg_result);
|
|
update_n(reg_result);
|
|
};
|
|
|
|
exec_and() is {
|
|
reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
|
|
update_z(reg_a);
|
|
update_n(reg_a);
|
|
reg_result = reg_a;
|
|
};
|
|
|
|
exec_sum() is {
|
|
update_c(reg_a, inst.alu_a);
|
|
reg_a = reg_a + inst.alu_a;
|
|
update_z(reg_a);
|
|
update_n(reg_a);
|
|
reg_result = reg_a;
|
|
//print me;
|
|
//dut_error();
|
|
};
|
|
|
|
update_z(arg : byte) is {
|
|
if (arg == 0) {
|
|
reg_status[1:1] = 1;
|
|
}
|
|
else {
|
|
reg_status[1:1] = 0;
|
|
}
|
|
};
|
|
|
|
update_c(arg1 : byte, arg2 : byte) is {
|
|
if (arg1 + arg2 > 256) {
|
|
reg_status[0:0] = 1;
|
|
}
|
|
else {
|
|
reg_status[0:0] = 0;
|
|
}
|
|
};
|
|
|
|
update_n(arg : byte) is {
|
|
if (arg[7:7] == 1) {
|
|
reg_status[7:7] = 1;
|
|
}
|
|
else {
|
|
reg_status[7:7] = 0;
|
|
}
|
|
};
|
|
};
|
|
'>
|
|
|
|
No newline at end of file
|
No newline at end of file
|
|
if (reg_x != alu_x) {
|
|
dut_error("WRONG!");
|
|
};
|
|
|
|
if (reg_y != alu_y) {
|
|
dut_error("WRONG!");
|
|
};
|
|
|
|
if (reg_status != alu_status) {
|
|
dut_error("WRONG!");
|
|
};
|
|
//};
|
|
}
|
|
};
|
|
|
|
execute() is {
|
|
case inst.alu_opcode {
|
|
ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
|
|
ADC_ZPG: { exec_sum(); };
|
|
ADC_ZPX: { exec_sum(); };
|
|
ADC_ABS: { exec_sum(); };
|
|
ADC_ABX: { exec_sum(); };
|
|
ADC_ABY: { exec_sum(); };
|
|
ADC_IDX: { exec_sum(); };
|
|
ADC_IDY: { exec_sum(); };
|
|
|
|
AND_IMM: { exec_and(); }; // A,Z,N = A&M
|
|
AND_ZPG: { exec_and(); };
|
|
AND_ZPX: { exec_and(); };
|
|
AND_ABS: { exec_and(); };
|
|
AND_ABX: { exec_and(); };
|
|
AND_ABY: { exec_and(); };
|
|
AND_IDX: { exec_and(); };
|
|
AND_IDY: { exec_and(); };
|
|
|
|
ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
|
|
|
|
ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
|
|
ASL_ZPX: { exec_asl_mem(); };
|
|
ASL_ABS: { exec_asl_mem(); };
|
|
ASL_ABX: { exec_asl_mem(); };
|
|
|
|
default: {
|
|
//dut_error("unknown opcode");
|
|
}
|
|
};
|
|
};
|
|
|
|
exec_asl_acc() is {
|
|
reg_status[0:0] = reg_a[7:7];
|
|
reg_a = reg_a * 2;
|
|
update_z(reg_a);
|
|
update_n(reg_a);
|
|
reg_result = reg_a;
|
|
};
|
|
|
|
exec_asl_mem() is {
|
|
reg_status[0:0] = inst.alu_a[7:7];
|
|
reg_result = inst.alu_a * 2;
|
|
update_z(reg_result);
|
|
update_n(reg_result);
|
|
};
|
|
|
|
exec_and() is {
|
|
reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
|
|
update_z(reg_a);
|
|
update_n(reg_a);
|
|
reg_result = reg_a;
|
|
};
|
|
|
|
exec_sum() is {
|
|
update_c(reg_a, inst.alu_a, reg_status[0:0]);
|
|
reg_a = reg_a + inst.alu_a + reg_status[0:0];
|
|
update_z(reg_a);
|
|
update_n(reg_a);
|
|
reg_result = reg_a;
|
|
//print me;
|
|
//dut_error();
|
|
};
|
|
|
|
update_z(arg : byte) is {
|
|
if (arg == 0) {
|
|
reg_status[1:1] = 1;
|
|
}
|
|
else {
|
|
reg_status[1:1] = 0;
|
|
}
|
|
};
|
|
|
|
update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
|
|
if (arg1 + arg2 + arg3 > 256) {
|
|
reg_status[0:0] = 1;
|
|
}
|
|
else {
|
|
reg_status[0:0] = 0;
|
|
}
|
|
};
|
|
|
|
update_n(arg : byte) is {
|
|
if (arg[7:7] == 1) {
|
|
reg_status[7:7] = 1;
|
|
}
|
|
else {
|
|
reg_status[7:7] = 0;
|
|
}
|
|
};
|
|
};
|
|
'>
|
|
|
No newline at end of file
|
No newline at end of file
|
