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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Diff between revs 144 and 146

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Rev 144 Rev 146
Line 59... Line 59...
                                };
                                };
                                DISABLED_VALID: {
                                DISABLED_VALID: {
                                        out("CYCLE ", count_cycles, ": just comparing");
                                        out("CYCLE ", count_cycles, ": just comparing");
                                };
                                };
                                RESET: {
                                RESET: {
 
                                        reg_x = 0;
 
                                        reg_y = 0;
 
                                        reg_status = 8'b00100010;
 
                                        reg_a = 0; // TODO: check this
 
                                        reg_result = 0;
 
 
                                        return;
                                        return;
                                };
                                };
                                default: {
                                default: {
                                        dut_error("error at e code");
                                        dut_error("error at e code");
                                };
                                };
                        };
                        };
 
 
                        // here i have already calculated. must compare!
                        // here i have already calculated. must compare!
 
 
                        //if (count_cycles > 3) {
                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
                        if (reg_result != alu_result) {
 
                                print inst;
                                print inst;
                                print me;
                                print me;
                                print alu_result;
                                print alu_result;
                                print alu_status;
                                print alu_status;
                                print alu_x;
                                print alu_x;
                                print alu_y;
                                print alu_y;
 
 
                                dut_error("WRONG!");
                                dut_error("WRONG!");
                        };
                        };
 
                };
                        if (reg_x != alu_x) {
        };
                                dut_error("WRONG!");
 
                        };
        execute() is {
 
                case inst.alu_opcode {
                        if (reg_y != alu_y) {
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
                                dut_error("WRONG!");
                        ADC_ZPG: { exec_sum(); };
                        };
                        ADC_ZPX: { exec_sum(); };
 
                        ADC_ABS: { exec_sum(); };
                        if (reg_status != alu_status) {
                        ADC_ABX: { exec_sum(); };
                                dut_error("WRONG!");
                        ADC_ABY: { exec_sum(); };
                        };
                        ADC_IDX: { exec_sum(); };
                        //};
                        ADC_IDY: { exec_sum(); };
                }
 
        };
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
 
                        AND_ZPG: { exec_and(); };
        execute() is {
                        AND_ZPX: { exec_and(); };
                case inst.alu_opcode {
                        AND_ABS: { exec_and(); };
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
                        AND_ABX: { exec_and(); };
                        ADC_ZPG: { exec_sum(); };
                        AND_ABY: { exec_and(); };
                        ADC_ZPX: { exec_sum(); };
                        AND_IDX: { exec_and(); };
                        ADC_ABS: { exec_sum(); };
                        AND_IDY: { exec_and(); };
                        ADC_ABX: { exec_sum(); };
 
                        ADC_ABY: { exec_sum(); };
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
                        ADC_IDX: { exec_sum(); };
 
                        ADC_IDY: { exec_sum(); };
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
 
                        ASL_ZPX: { exec_asl_mem(); };
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
                        ASL_ABS: { exec_asl_mem(); };
                        AND_ZPG: { exec_and(); };
                        ASL_ABX: { exec_asl_mem(); };
                        AND_ZPX: { exec_and(); };
 
                        AND_ABS: { exec_and(); };
                        default: {
                        AND_ABX: { exec_and(); };
                                //dut_error("unknown opcode");
                        AND_ABY: { exec_and(); };
                        }
                        AND_IDX: { exec_and(); };
                };
                        AND_IDY: { exec_and(); };
        };
 
 
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
        exec_asl_acc() is {
 
                reg_status[0:0] = reg_a[7:7];
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
                reg_a = reg_a * 2;
                        ASL_ZPX: { exec_asl_mem(); };
                update_z(reg_a);
                        ASL_ABS: { exec_asl_mem(); };
                update_n(reg_a);
                        ASL_ABX: { exec_asl_mem(); };
                reg_result = reg_a;
 
        };
                        default: {
 
                                //dut_error("unknown opcode");
        exec_asl_mem() is {
                        }
                reg_status[0:0] = inst.alu_a[7:7];
                };
                reg_result = inst.alu_a * 2;
        };
                update_z(reg_result);
 
                update_n(reg_result);
 
        };
 
 
 
        exec_and() is {
 
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
 
                update_z(reg_a);
 
                update_n(reg_a);
 
                reg_result = reg_a;
 
        };
 
 
 
        exec_sum() is {
 
                out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
 
                reg_result = reg_a + inst.alu_a + reg_status[0:0];
 
                update_c(reg_a, inst.alu_a, reg_status[0:0]);
 
                update_v(reg_a, inst.alu_a, reg_result);
 
                update_z(reg_result);
 
                update_n(reg_result);
 
                reg_a = reg_result;
 
                //print me;
 
                //dut_error();
 
        };
 
 
 
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
 
                if (arg1 + arg2 + arg3 > 256) {
 
                        reg_status[0:0] = 1;
 
                }
 
                else {
 
                        reg_status[0:0] = 0;
 
                }
 
        };
 
 
 
        update_v(op1 : byte, op2 : byte, res : byte) is {
 
                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
 
                        reg_status[6:6] = 1;
 
                }
 
                else {
 
                        reg_status[6:6] = 0;
 
                };
 
        };
 
 
 
        update_z(arg : byte) is {
 
                if (arg == 0) {
 
                        reg_status[1:1] = 1;
 
                }
 
                else {
 
                        reg_status[1:1] = 0;
 
                }
 
        };
 
 
 
 
 
        update_n(arg : byte) is {
 
                if (arg[7:7] == 1) {
 
                        reg_status[7:7] = 1;
 
                }
 
                else {
 
                        reg_status[7:7] = 0;
 
                }
 
        };
 
};
 
'>
 
 
        exec_asl_acc() is {
 
                reg_status[0:0] = reg_a[7:7];
 
                reg_a = reg_a * 2;
 
                update_z(reg_a);
 
                update_n(reg_a);
 
                reg_result = reg_a;
 
        };
 
 
 
        exec_asl_mem() is {
 
                reg_status[0:0] = inst.alu_a[7:7];
 
                reg_result = inst.alu_a * 2;
 
                update_z(reg_result);
 
                update_n(reg_result);
 
        };
 
 
 
        exec_and() is {
 
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
 
                update_z(reg_a);
 
                update_n(reg_a);
 
                reg_result = reg_a;
 
        };
 
 
 
        exec_sum() is {
 
                reg_result = reg_a + inst.alu_a + reg_status[0:0];
 
                update_c(reg_a, inst.alu_a, reg_status[0:0]);
 
                update_z(reg_result);
 
                update_n(reg_result);
 
                reg_a = reg_result;
 
                //print me;
 
                //dut_error();
 
        };
 
 
 
        update_z(arg : byte) is {
 
                if (arg == 0) {
 
                        reg_status[1:1] = 1;
 
                }
 
                else {
 
                        reg_status[1:1] = 0;
 
                }
 
        };
 
 
 
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
 
                if (arg1 + arg2 + arg3 > 256) {
 
                        reg_status[0:0] = 1;
 
                }
 
                else {
 
                        reg_status[0:0] = 0;
 
                }
 
        };
 
 
 
        update_n(arg : byte) is {
 
                if (arg[7:7] == 1) {
 
                        reg_status[7:7] = 1;
 
                }
 
                else {
 
                        reg_status[7:7] = 0;
 
                }
 
        };
 
};
 
'>
 
 
 
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