Line 73... |
Line 73... |
// here i have already calculated. must compare!
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// here i have already calculated. must compare!
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if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
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if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
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out("#########################################################");
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out("#########################################################");
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print me;
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print me;
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print me.inst;
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out("#########################################################");
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out("#########################################################");
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print alu_result;
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print alu_result;
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print alu_status;
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print alu_status;
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print alu_x;
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print alu_x;
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print alu_y;
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print alu_y;
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Line 111... |
Line 112... |
ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
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ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
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ASL_ZPX: { exec_asl_mem(); };
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ASL_ZPX: { exec_asl_mem(); };
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ASL_ABS: { exec_asl_mem(); };
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ASL_ABS: { exec_asl_mem(); };
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ASL_ABX: { exec_asl_mem(); };
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ASL_ABX: { exec_asl_mem(); };
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BCC_REL: {};
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BCC_REL: {}; // nothing is done. these are all branches.
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BCS_REL: {};
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BCS_REL: {};
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BEQ_REL: {};
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BEQ_REL: {};
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BMI_REL: {};
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BNE_REL: {};
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BPL_REL: {};
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BVC_REL: {};
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BVS_REL: {};
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BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
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BIT_ABS: { exec_bit(); };
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BRK_IMP: { reg_status[4:4] = 1; };
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CLC_IMP: { reg_status[0:0] = 0; };
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CLD_IMP: { reg_status[3:3] = 0; };
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CLI_IMP: { reg_status[2:2] = 0; };
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CLV_IMP: { reg_status[6:6] = 0; };
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|
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default: {
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default: {
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//dut_error("unknown opcode");
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out(inst.alu_opcode);
|
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dut_error("unknown opcode");
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}
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}
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};
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};
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};
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};
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|
|
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exec_bit() is {
|
|
update_z(reg_a & inst.alu_a);
|
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reg_status[7:7] = inst.alu_a[7:7];
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reg_status[6:6] = inst.alu_a[6:6];
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};
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|
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exec_asl_acc() is {
|
exec_asl_acc() is {
|
reg_status[0:0] = reg_a[7:7];
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reg_status[0:0] = reg_a[7:7];
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reg_a = reg_a * 2;
|
reg_a = reg_a * 2;
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update_z(reg_a);
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update_z(reg_a);
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update_n(reg_a);
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update_n(reg_a);
|