| Line 7... |
Line 7... |
reg_x : byte;
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reg_x : byte;
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reg_y : byte;
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reg_y : byte;
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reg_status : byte;
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reg_status : byte;
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reg_result : byte;
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reg_result : byte;
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inst : alu_input_s;
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!inst : alu_input_s;
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next_inst : alu_input_s;
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!next_inst : alu_input_s;
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count_cycles : int;
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count_cycles : int;
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first_cycle : bool;
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first_cycle : bool;
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last_a : byte;
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last_status : byte;
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last_result : byte;
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keep first_cycle == TRUE;
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keep first_cycle == TRUE;
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keep count_cycles == 0;
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keep count_cycles == 0;
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store(input : alu_input_s) is {
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store(input : alu_input_s) is {
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count_cycles = count_cycles + 1;
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count_cycles = count_cycles + 1;
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//out ("CYCLE ", count_cycles, " STORE:");
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//out ("CYCLE ", count_cycles, " STORE:");
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//print input;
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//print input;
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last_a = reg_a;
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last_status = reg_status;
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last_result = reg_result;
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if (first_cycle) {
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if (first_cycle) {
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inst = input;
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inst = input;
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next_inst = input;
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next_inst = input;
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}
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}
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else {
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else {
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| Line 46... |
Line 53... |
}
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}
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else {
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else {
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//out ("CYCLE ", count_cycles, " COMPARE:");
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//out ("CYCLE ", count_cycles, " COMPARE:");
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//print inst;
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//print inst;
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if (count_cycles == 99999) {
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out("ENOUGH!");
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stop_run();
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};
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case inst.input_kind {
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case inst.input_kind {
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ENABLED_VALID: {
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ENABLED_VALID: {
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//out("CYCLE ", count_cycles, ": executing and comparing");
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//out("CYCLE ", count_cycles, ": executing and comparing");
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execute();
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execute();
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};
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};
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| Line 131... |
Line 143... |
CLC_IMP: { reg_status[0:0] = 0; };
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CLC_IMP: { reg_status[0:0] = 0; };
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CLD_IMP: { reg_status[3:3] = 0; };
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CLD_IMP: { reg_status[3:3] = 0; };
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CLI_IMP: { reg_status[2:2] = 0; };
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CLI_IMP: { reg_status[2:2] = 0; };
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CLV_IMP: { reg_status[6:6] = 0; };
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CLV_IMP: { reg_status[6:6] = 0; };
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CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
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CMP_ZPG: { exec_cmp(reg_a); };
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CMP_ZPX: { exec_cmp(reg_a); };
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CMP_ABS: { exec_cmp(reg_a); };
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CMP_ABX: { exec_cmp(reg_a); };
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CMP_ABY: { exec_cmp(reg_a); };
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CMP_IDX: { exec_cmp(reg_a); };
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CMP_IDY: { exec_cmp(reg_a); };
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CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
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CPX_ZPG: { exec_cmp(reg_x); };
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CPX_ABS: { exec_cmp(reg_x); };
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CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
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CPY_ZPG: { exec_cmp(reg_y); };
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CPY_ABS: { exec_cmp(reg_y); };
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DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
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DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
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DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
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DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
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DEX_IMP: { exec_dec(reg_x, FALSE); }; // X,Z,N = X-1
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DEY_IMP: { exec_dec(reg_y, FALSE); }; // Y,Z,N = Y-1
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EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
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EOR_ZPG: { exec_eor(); };
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EOR_ZPX: { exec_eor(); };
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EOR_ABS: { exec_eor(); };
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EOR_ABX: { exec_eor(); };
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EOR_ABY: { exec_eor(); };
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EOR_IDX: { exec_eor(); };
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EOR_IDY: { exec_eor(); };
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INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
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INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
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INC_ABS: { exec_inc(inst.alu_a, TRUE); };
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INC_ABX: { exec_inc(inst.alu_a, TRUE); };
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INX_IMP: { exec_inc(reg_x, FALSE); };
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INY_IMP: { exec_inc(reg_y, FALSE); };
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JMP_ABS: {};
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JMP_IND: {};
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JSR_ABS: {};
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LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
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LDA_ZPG: { exec_load(reg_a, TRUE); };
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LDA_ZPX: { exec_load(reg_a, TRUE); };
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LDA_ABS: { exec_load(reg_a, TRUE); };
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LDA_ABX: { exec_load(reg_a, TRUE); };
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LDA_ABY: { exec_load(reg_a, TRUE); };
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LDA_IDX: { exec_load(reg_a, TRUE); };
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LDA_IDY: { exec_load(reg_a, TRUE); };
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LDX_IMM: { exec_load(reg_x, FALSE); };
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LDX_ZPG: { exec_load(reg_x, FALSE); };
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LDX_ZPY: { exec_load(reg_x, FALSE); };
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LDX_ABS: { exec_load(reg_x, FALSE); };
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LDX_ABY: { exec_load(reg_x, FALSE); };
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LDY_IMM: { exec_load(reg_y, FALSE); };
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LDY_ZPG: { exec_load(reg_y, FALSE); };
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LDY_ZPX: { exec_load(reg_y, FALSE); };
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LDY_ABS: { exec_load(reg_y, FALSE); };
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LDY_ABX: { exec_load(reg_y, FALSE); };
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LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
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LSR_ZPG: { exec_lsr(inst.alu_a); };
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LSR_ZPX: { exec_lsr(inst.alu_a); };
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LSR_ABS: { exec_lsr(inst.alu_a); };
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LSR_ABX: { exec_lsr(inst.alu_a); };
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NOP_IMP: {};
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ORA_IMM: { exec_or(); }; // A,Z,N = A|M
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ORA_ZPG: { exec_or(); };
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ORA_ZPX: { exec_or(); };
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ORA_ABS: { exec_or(); };
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ORA_ABX: { exec_or(); };
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ORA_ABY: { exec_or(); };
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ORA_IDX: { exec_or(); };
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ORA_IDY: { exec_or(); };
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PHA_IMP: { reg_result = reg_a; };
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PHP_IMP: {}; // P is always connected and the result is not updated
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PLA_IMP: {
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reg_a = inst.alu_a;
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reg_result = inst.alu_a;
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update_z(reg_a);
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update_n(reg_a);
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};
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PLP_IMP: {
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reg_status = inst.alu_a;
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reg_status[5:5] = 1; // this is always one
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};
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default: {
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default: {
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out(inst.alu_opcode);
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out(inst.alu_opcode);
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dut_error("unknown opcode");
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dut_error("unknown opcode");
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}
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}
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};
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};
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};
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};
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exec_or() is {
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reg_a = reg_a | inst.alu_a;
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reg_result = reg_a;
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update_z(reg_a);
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update_n(reg_a);
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};
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exec_lsr(arg1 : *byte) is {
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reg_status[0:0] = arg1[0:0];
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arg1 = arg1 >> 1;
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update_z(arg1);
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update_n(arg1);
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reg_result = arg1;
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};
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exec_load(arg1 : *byte, update_result : bool) is {
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arg1 = inst.alu_a;
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if (update_result) { //
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reg_result = inst.alu_a; // no need for this but...
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};
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update_z(arg1);
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update_n(arg1);
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};
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exec_inc(arg1 : *byte, update_result : bool) is {
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arg1 = arg1 + 1;
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update_z(arg1);
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update_n(arg1);
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if (update_result) { //
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reg_result = arg1;
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};
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};
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exec_eor() is {
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reg_a = reg_a ^ inst.alu_a;
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reg_result = reg_a;
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update_z(reg_a);
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update_n(reg_a);
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};
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exec_dec(arg1 : *byte, update_result : bool) is {
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arg1 = arg1 - 1;
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update_z(arg1);
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update_n(arg1);
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if (update_result) { // DEX and DEY do not output the result
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reg_result = arg1;
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};
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};
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exec_cmp(arg1 : byte) is {
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update_z(arg1 - inst.alu_a);
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update_n(arg1 - inst.alu_a);
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if (arg1 >= inst.alu_a) {
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reg_status[0:0] = 1;
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}
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else {
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reg_status[0:0] = 0;
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};
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};
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exec_bit() is {
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exec_bit() is {
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update_z(reg_a & inst.alu_a);
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update_z(reg_a & inst.alu_a);
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reg_status[7:7] = inst.alu_a[7:7];
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reg_status[7:7] = inst.alu_a[7:7];
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reg_status[6:6] = inst.alu_a[6:6];
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reg_status[6:6] = inst.alu_a[6:6];
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};
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};
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