| Line 240... |
Line 240... |
PLP_IMP: {
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PLP_IMP: {
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reg_status = inst.alu_a;
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reg_status = inst.alu_a;
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reg_status[5:5] = 1; // this is always one
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reg_status[5:5] = 1; // this is always one
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};
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};
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|
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//ROL_ACC: { exec_rol(reg_a); };
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//ROL_ZPG: { exec_rol(inst.alu_a); };
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//ROL_ZPX: { exec_rol(inst.alu_a); };
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//ROL_ABS: { exec_rol(inst.alu_a); };
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//ROL_ABX: { exec_rol(inst.alu_a); };
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|
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default: {
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default: {
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out(inst.alu_opcode);
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out(inst.alu_opcode);
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dut_error("unknown opcode");
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dut_error("unknown opcode");
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}
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}
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};
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};
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};
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};
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|
|
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exec_rol(arg1 : *byte) is {
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var oldcarry : bit;
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|
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oldcarry = reg_status[0:0];
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reg_status[0:0] = arg1[7:7];
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arg1 = arg1 << 1;
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arg1[0:0] = oldcarry;
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|
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reg_result = reg_a;
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update_z(reg_a);
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update_n(reg_a);
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};
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|
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exec_or() is {
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exec_or() is {
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reg_a = reg_a | inst.alu_a;
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reg_a = reg_a | inst.alu_a;
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reg_result = reg_a;
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reg_result = reg_a;
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update_z(reg_a);
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update_z(reg_a);
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update_n(reg_a);
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update_n(reg_a);
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| Line 341... |
Line 360... |
reg_result = reg_a;
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reg_result = reg_a;
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};
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};
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|
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exec_sum() is {
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exec_sum() is {
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//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
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//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
|
|
if (reg_status[3:3] == 1) {
|
|
var op1 : byte;
|
|
var op2 : byte;
|
|
|
|
op1 = inst.alu_a[3:0];
|
|
op2 = inst.alu_a[7:4];
|
|
|
|
print op1;
|
|
print op2;
|
|
|
|
op1 = reg_a[3:0] + op1 + reg_status[0:0];
|
|
op2 = reg_a[7:4] + op2;
|
|
|
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if (op1 >= 10) {
|
|
op1 = op1 % 10;
|
|
op2 = op2 + 1;
|
|
};
|
|
|
|
if (op2 >= 10) {
|
|
op2 = op2 % 10;
|
|
reg_status[0:0] = 1;
|
|
}
|
|
else {
|
|
reg_status[0:0] = 0;
|
|
};
|
|
|
|
reg_result[3:0] = op1;
|
|
reg_result[7:4] = op2;
|
|
update_z(reg_result);
|
|
update_n(reg_result);
|
|
reg_a = reg_result;
|
|
}
|
|
else {
|
reg_result = reg_a + inst.alu_a + reg_status[0:0];
|
reg_result = reg_a + inst.alu_a + reg_status[0:0];
|
update_c(reg_a, inst.alu_a, reg_status[0:0]);
|
update_c(reg_a, inst.alu_a, reg_status[0:0]);
|
update_v(reg_a, inst.alu_a, reg_result);
|
update_v(reg_a, inst.alu_a, reg_result);
|
update_z(reg_result);
|
update_z(reg_result);
|
update_n(reg_result);
|
update_n(reg_result);
|
reg_a = reg_result;
|
reg_a = reg_result;
|
//print me;
|
};
|
//dut_error();
|
|
};
|
};
|
|
|
update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
|
update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
|
if (arg1 + arg2 + arg3 > 255) {
|
if (arg1 + arg2 + arg3 > 255) {
|
reg_status[0:0] = 1;
|
reg_status[0:0] = 1;
|
