| Line 240... |
Line 240... |
PLP_IMP: {
|
PLP_IMP: {
|
reg_status = inst.alu_a;
|
reg_status = inst.alu_a;
|
reg_status[5:5] = 1; // this is always one
|
reg_status[5:5] = 1; // this is always one
|
};
|
};
|
|
|
//ROL_ACC: { exec_rol(reg_a); };
|
ROL_ACC: { exec_rol(reg_a); };
|
//ROL_ZPG: { exec_rol(inst.alu_a); };
|
ROL_ZPG: { exec_rol(inst.alu_a); };
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//ROL_ZPX: { exec_rol(inst.alu_a); };
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ROL_ZPX: { exec_rol(inst.alu_a); };
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//ROL_ABS: { exec_rol(inst.alu_a); };
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ROL_ABS: { exec_rol(inst.alu_a); };
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//ROL_ABX: { exec_rol(inst.alu_a); };
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ROL_ABX: { exec_rol(inst.alu_a); };
|
|
|
default: {
|
default: {
|
out(inst.alu_opcode);
|
out(inst.alu_opcode);
|
dut_error("unknown opcode");
|
dut_error("unknown opcode");
|
}
|
}
|
| Line 261... |
Line 261... |
oldcarry = reg_status[0:0];
|
oldcarry = reg_status[0:0];
|
reg_status[0:0] = arg1[7:7];
|
reg_status[0:0] = arg1[7:7];
|
arg1 = arg1 << 1;
|
arg1 = arg1 << 1;
|
arg1[0:0] = oldcarry;
|
arg1[0:0] = oldcarry;
|
|
|
reg_result = reg_a;
|
reg_result = arg1;
|
update_z(reg_a);
|
update_z(arg1);
|
update_n(reg_a);
|
update_n(arg1);
|
};
|
};
|
|
|
exec_or() is {
|
exec_or() is {
|
reg_a = reg_a | inst.alu_a;
|
reg_a = reg_a | inst.alu_a;
|
reg_result = reg_a;
|
reg_result = reg_a;
|
| Line 364... |
Line 364... |
//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
|
//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
|
if (reg_status[3:3] == 1) {
|
if (reg_status[3:3] == 1) {
|
var op1 : byte;
|
var op1 : byte;
|
var op2 : byte;
|
var op2 : byte;
|
|
|
|
out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
|
|
op1 = inst.alu_a[3:0];
|
op1 = inst.alu_a[3:0];
|
op2 = inst.alu_a[7:4];
|
op2 = inst.alu_a[7:4];
|
|
|
print op1;
|
print op1;
|
print op2;
|
print op2;
|
|
|
op1 = reg_a[3:0] + op1 + reg_status[0:0];
|
op1 = reg_a[3:0] + op1 + reg_status[0:0];
|
op2 = reg_a[7:4] + op2;
|
op2 = reg_a[7:4] + op2;
|
|
|
|
print op1;
|
|
print op2;
|
|
|
if (op1 >= 10) {
|
if (op1 >= 10) {
|
|
op2 = op2 + op1/ 10;
|
op1 = op1 % 10;
|
op1 = op1 % 10;
|
op2 = op2 + 1;
|
|
};
|
};
|
|
|
|
print op1;
|
|
print op2;
|
|
|
if (op2 >= 10) {
|
if (op2 >= 10) {
|
op2 = op2 % 10;
|
op2 = op2 % 10;
|
reg_status[0:0] = 1;
|
reg_status[0:0] = 1;
|
}
|
}
|
else {
|
else {
|
