| Line 240... |
Line 240... |
PLP_IMP: {
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PLP_IMP: {
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reg_status = inst.alu_a;
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reg_status = inst.alu_a;
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reg_status[5:5] = 1; // this is always one
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reg_status[5:5] = 1; // this is always one
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};
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};
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ROL_ACC: { exec_rol(reg_a); };
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ROL_ACC: { exec_rot(TRUE, reg_a); };
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ROL_ZPG: { exec_rol(inst.alu_a); };
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ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
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ROL_ZPX: { exec_rol(inst.alu_a); };
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ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
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ROL_ABS: { exec_rol(inst.alu_a); };
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ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
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ROL_ABX: { exec_rol(inst.alu_a); };
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ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
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ROR_ACC: { exec_rot(FALSE, reg_a); };
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ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
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ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
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ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
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ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
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RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
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RTS_IMP: { };
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SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
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SBC_ZPG: { exec_sub(); };
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SBC_ZPX: { exec_sub(); };
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SBC_ABS: { exec_sub(); };
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SBC_ABX: { exec_sub(); };
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SBC_ABY: { exec_sub(); };
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SBC_IDX: { exec_sub(); };
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SBC_IDY: { exec_sub(); };
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SEC_IMP: { reg_status[0:0] = 1; };
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SED_IMP: { reg_status[3:3] = 1; };
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SEI_IMP: { reg_status[2:2] = 1; };
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STA_ZPG: { reg_result = reg_a; };
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STA_ZPX: { reg_result = reg_a; };
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STA_ABS: { reg_result = reg_a; };
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STA_ABX: { reg_result = reg_a; };
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STA_ABY: { reg_result = reg_a; };
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STA_IDX: { reg_result = reg_a; };
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STA_IDY: { reg_result = reg_a; };
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//STX_ZPG: { reg_result = reg_x; };
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//STX_ZPY: { reg_result = reg_x; };
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//STX_ABS: { reg_result = reg_x; };
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//STY_ZPG: { reg_result = reg_y; };
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//STY_ZPX: { reg_result = reg_y; };
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//STY_ABS: { reg_result = reg_y; };
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//TAX_IMP: { exec_transfer(reg_a, reg_x); };
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//TAY_IMP: { exec_transfer(reg_a, reg_y); };
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//TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
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//TXA_IMP: { exec_transfer(reg_x, reg_a); };
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//TXS_IMP: { };
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//TYA_IMP: { exec_transfer(reg_y, reg_a); };
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default: {
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default: {
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out(inst.alu_opcode);
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out(inst.alu_opcode);
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dut_error("unknown opcode");
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dut_error("unknown opcode");
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}
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}
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};
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};
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};
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};
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exec_rol(arg1 : *byte) is {
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exec_transfer(source : byte, dest : *byte) is {
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dest = source;
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update_z(dest);
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update_n(dest);
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};
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exec_sub() is {
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if (reg_status[3:3] == 1) {
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var op1 : int;
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var op2 : int;
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//out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
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op1 = inst.alu_a[3:0];
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op2 = inst.alu_a[7:4];
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op1 = reg_a[3:0] - op1 -1 + reg_status[0:0];
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op2 = reg_a[7:4] - op2;
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if (op1 >= 10) {
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op2 = op2 + op1/10;
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op1 = op1 % 10;
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} else if (op1 < 0) {
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op2 = op2 - op1/10;
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op1 = -(op1 % 10);
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};
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|
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if (op2 >= 10) {
|
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op2 = op2 % 10;
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reg_status[0:0] = 1;
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}
|
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else if (op2 < 0) {
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op2 = op2 + 10;
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reg_status[0:0] = 0;
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};
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|
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reg_result[3:0] = op1;
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reg_result[7:4] = op2;
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}
|
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else {
|
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reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
|
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if (reg_result[7:7] == 1) {
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reg_status[0:0] = 0;
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}
|
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else {
|
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reg_status[0:0] = 1;
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};
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};
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|
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update_z(reg_result);
|
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update_n(reg_result);
|
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update_v(reg_a, inst.alu_a, reg_result);
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|
|
reg_a = reg_result;
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|
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};
|
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|
|
exec_rot(left : bool, arg1 : *byte) is {
|
var oldcarry : bit;
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var oldcarry : bit;
|
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|
|
if (left) {
|
oldcarry = reg_status[0:0];
|
oldcarry = reg_status[0:0];
|
reg_status[0:0] = arg1[7:7];
|
reg_status[0:0] = arg1[7:7];
|
arg1 = arg1 << 1;
|
arg1 = arg1 << 1;
|
arg1[0:0] = oldcarry;
|
arg1[0:0] = oldcarry;
|
|
}
|
|
else {
|
|
oldcarry = reg_status[0:0];
|
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reg_status[0:0] = arg1[0:0];
|
|
arg1 = arg1 >> 1;
|
|
arg1[7:7] = oldcarry;
|
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};
|
|
|
reg_result = arg1;
|
reg_result = arg1;
|
update_z(arg1);
|
update_z(arg1);
|
update_n(arg1);
|
update_n(arg1);
|
};
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};
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| Line 364... |
Line 472... |
//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
|
//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
|
if (reg_status[3:3] == 1) {
|
if (reg_status[3:3] == 1) {
|
var op1 : byte;
|
var op1 : byte;
|
var op2 : byte;
|
var op2 : byte;
|
|
|
out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
//out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
|
|
op1 = inst.alu_a[3:0];
|
op1 = inst.alu_a[3:0];
|
op2 = inst.alu_a[7:4];
|
op2 = inst.alu_a[7:4];
|
|
|
print op1;
|
|
print op2;
|
|
|
|
op1 = reg_a[3:0] + op1 + reg_status[0:0];
|
op1 = reg_a[3:0] + op1 + reg_status[0:0];
|
op2 = reg_a[7:4] + op2;
|
op2 = reg_a[7:4] + op2;
|
|
|
print op1;
|
|
print op2;
|
|
|
|
if (op1 >= 10) {
|
if (op1 >= 10) {
|
op2 = op2 + op1/ 10;
|
op2 = op2 + op1/ 10;
|
op1 = op1 % 10;
|
op1 = op1 % 10;
|
};
|
};
|
|
|
print op1;
|
|
print op2;
|
|
|
|
if (op2 >= 10) {
|
if (op2 >= 10) {
|
op2 = op2 % 10;
|
op2 = op2 % 10;
|
reg_status[0:0] = 1;
|
reg_status[0:0] = 1;
|
}
|
}
|
else {
|
else {
|
| Line 398... |
Line 497... |
|
|
reg_result[3:0] = op1;
|
reg_result[3:0] = op1;
|
reg_result[7:4] = op2;
|
reg_result[7:4] = op2;
|
update_z(reg_result);
|
update_z(reg_result);
|
update_n(reg_result);
|
update_n(reg_result);
|
|
update_v(reg_a, inst.alu_a, reg_result);
|
reg_a = reg_result;
|
reg_a = reg_result;
|
}
|
}
|
else {
|
else {
|
reg_result = reg_a + inst.alu_a + reg_status[0:0];
|
reg_result = reg_a + inst.alu_a + reg_status[0:0];
|
update_c(reg_a, inst.alu_a, reg_status[0:0]);
|
update_c(reg_a, inst.alu_a, reg_status[0:0]);
|
