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[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Diff between revs 177 and 182

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Rev 177 Rev 182
Line 15... Line 15...
        count_cycles : int;
        count_cycles : int;
        first_cycle : bool;
        first_cycle : bool;
        last_a : byte;
        last_a : byte;
        last_status : byte;
        last_status : byte;
        last_result : byte;
        last_result : byte;
 
        rst_counter : byte;
 
 
        keep first_cycle == TRUE;
        keep first_cycle == TRUE;
        keep count_cycles == 0;
        keep count_cycles == 0;
 
        keep rst_counter == 0;
 
 
 
        event T3_cover_event;
 
        cover T3_cover_event is {
 
                item rst_counter; // using num_of_buckets=100;
 
        };
 
 
 
 
        store(input : alu_input_s) is {
        store(input : alu_input_s) is {
                count_cycles = count_cycles + 1;
                count_cycles = count_cycles + 1;
 
 
                //out ("CYCLE ", count_cycles, " STORE:");
                //out ("CYCLE ", count_cycles, " STORE:");
Line 50... Line 58...
                        reg_status = 8'b00100010;
                        reg_status = 8'b00100010;
                        reg_a = 0; // TODO: check this
                        reg_a = 0; // TODO: check this
                        reg_result = 0;
                        reg_result = 0;
                }
                }
                else {
                else {
                        //out ("CYCLE ", count_cycles, " COMPARE:");
                        out ("CYCLE ", count_cycles, " COMPARE:");
                        //print inst;
                        print inst;
 
 
                        if (count_cycles == 99999) {
                        if (count_cycles == 99999) {
                                out("ENOUGH!");
                                out("ENOUGH!");
                                stop_run();
                                stop_run();
                        };
                        };
 
 
 
                        if (inst.input_kind == RESET) {
 
                                rst_counter = rst_counter + 1;
 
                        }
 
                        else {
 
                                emit T3_cover_event;
 
                                rst_counter = 0;
 
                        };
 
 
                        case inst.input_kind {
                        case inst.input_kind {
                                ENABLED_VALID: {
                                ENABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        execute();
                                        execute();
                                };
                                };
                                DISABLED_VALID: {
 
                                        //out("CYCLE ", count_cycles, ": just comparing");
 
                                };
 
                                RESET: {
                                RESET: {
                                        reg_x = 0;
                                        reg_x = 0;
                                        reg_y = 0;
                                        reg_y = 0;
                                        reg_status = 8'b00100010;
                                        reg_status = 8'b00100010;
                                        reg_a = 0; // TODO: check this
                                        reg_a = 0; // TODO: check this
                                        reg_result = 0;
                                        reg_result = 0;
 
 
                                        return;
                                        return;
                                };
                                };
 
                                ENABLED_RAND: {
 
                                        execute();
 
                                };
                                default: {
                                default: {
                                        dut_error("error at e code");
 
                                };
                                };
                        };
                        };
 
 
                        // here i have already calculated. must compare!
                        // here i have already calculated. must compare!
 
 
Line 274... Line 289...
                        STA_ABS: { reg_result = reg_a; };
                        STA_ABS: { reg_result = reg_a; };
                        STA_ABX: { reg_result = reg_a; };
                        STA_ABX: { reg_result = reg_a; };
                        STA_ABY: { reg_result = reg_a; };
                        STA_ABY: { reg_result = reg_a; };
                        STA_IDX: { reg_result = reg_a; };
                        STA_IDX: { reg_result = reg_a; };
                        STA_IDY: { reg_result = reg_a; };
                        STA_IDY: { reg_result = reg_a; };
                        //STX_ZPG: { reg_result = reg_x; };
                        STX_ZPG: { };
                        //STX_ZPY: { reg_result = reg_x; };
                        STX_ZPY: { };
                        //STX_ABS: { reg_result = reg_x; };
                        STX_ABS: { };
                        //STY_ZPG: { reg_result = reg_y; };
                        STY_ZPG: { };
                        //STY_ZPX: { reg_result = reg_y; };
                        STY_ZPX: { };
                        //STY_ABS: { reg_result = reg_y; };
                        STY_ABS: { };
 
 
                        //TAX_IMP: { exec_transfer(reg_a, reg_x); };
                        TAX_IMP: { exec_transfer(reg_a, reg_x); };
                        //TAY_IMP: { exec_transfer(reg_a, reg_y); };
                        TAY_IMP: { exec_transfer(reg_a, reg_y); };
                        //TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
                        TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
                        //TXA_IMP: { exec_transfer(reg_x, reg_a); };
                        TXA_IMP: { exec_transfer(reg_x, reg_a); };
                        //TXS_IMP: { };
                        TXS_IMP: { };
                        //TYA_IMP: { exec_transfer(reg_y, reg_a); };
                        TYA_IMP: { exec_transfer(reg_y, reg_a); reg_result = reg_y; }; // A = Y
 
 
                        default: {
                        default: {
                                out(inst.alu_opcode);
                                // all the random generated opcodes will fall here
                                dut_error("unknown opcode");
 
                        }
                        }
                };
                };
        };
        };
 
 
        exec_transfer(source : byte, dest : *byte) is {
        exec_transfer(source : byte, dest : *byte) is {
Line 322... Line 336...
                        } else if (op1 < 0) {
                        } else if (op1 < 0) {
                                op2 = op2 - op1/10;
                                op2 = op2 - op1/10;
                                op1 = -(op1 % 10);
                                op1 = -(op1 % 10);
                        };
                        };
 
 
 
                        reg_status[0:0] = 1;
 
 
                        if (op2 >= 10) {
                        if (op2 >= 10) {
                                op2 = op2 % 10;
                                op2 = op2 % 10;
                                reg_status[0:0] = 1;
 
                        }
                        }
                        else if (op2 < 0) {
                        else if (op2 < 0) {
                                op2 = op2 + 10;
                                op2 = op2 + 10;
                                reg_status[0:0] = 0;
                                reg_status[0:0] = 0;
                        };
                        };

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