| Line 54... |
Line 54... |
if (first_cycle) {
|
if (first_cycle) {
|
first_cycle = FALSE;
|
first_cycle = FALSE;
|
reg_x = 0;
|
reg_x = 0;
|
reg_y = 0;
|
reg_y = 0;
|
reg_status = 8'b00100010;
|
reg_status = 8'b00100010;
|
reg_a = 0; // TODO: check this
|
reg_a = 0;
|
reg_result = 0;
|
reg_result = 0;
|
}
|
}
|
else {
|
else {
|
out ("CYCLE ", count_cycles, " COMPARE:");
|
//out ("CYCLE ", count_cycles, " COMPARE:");
|
print inst;
|
//print inst;
|
|
|
if (count_cycles == 99999) {
|
if (count_cycles == 99999) {
|
out("ENOUGH!");
|
out("ENOUGH!");
|
stop_run();
|
stop_run();
|
};
|
};
|
| Line 77... |
Line 77... |
};
|
};
|
|
|
case inst.input_kind {
|
case inst.input_kind {
|
ENABLED_VALID: {
|
ENABLED_VALID: {
|
//out("CYCLE ", count_cycles, ": executing and comparing");
|
//out("CYCLE ", count_cycles, ": executing and comparing");
|
execute();
|
execute(inst.alu_opcode);
|
|
|
|
if (reg_status[3:3] == 1) {
|
|
case inst.alu_opcode {
|
|
SBC_IMM: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ZPG: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ZPX: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ABS: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ABX: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ABY: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_IDX: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_IDY: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
};
|
|
};
|
};
|
};
|
RESET: {
|
RESET: {
|
reg_x = 0;
|
reg_x = 0;
|
reg_y = 0;
|
reg_y = 0;
|
reg_status = 8'b00100010;
|
reg_status = 8'b00100010;
|
| Line 89... |
Line 134... |
reg_result = 0;
|
reg_result = 0;
|
|
|
return;
|
return;
|
};
|
};
|
ENABLED_RAND: {
|
ENABLED_RAND: {
|
execute();
|
execute(inst.rand_op.as_a(valid_opcodes));
|
|
|
|
if (reg_status[3:3] == 1) {
|
|
case inst.rand_op.as_a(valid_opcodes) {
|
|
SBC_IMM: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ZPG: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ZPX: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ABS: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ABX: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_ABY: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_IDX: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
SBC_IDY: {
|
|
reg_a = alu_result;
|
|
reg_result = alu_result;
|
|
reg_status = alu_status;
|
|
};
|
|
};
|
|
};
|
|
|
};
|
};
|
default: {
|
default: {
|
};
|
};
|
};
|
};
|
|
|
| Line 112... |
Line 203... |
dut_error("WRONG!");
|
dut_error("WRONG!");
|
};
|
};
|
};
|
};
|
};
|
};
|
|
|
execute() is {
|
execute(opcode : valid_opcodes) is {
|
case inst.alu_opcode {
|
case opcode {
|
ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
|
ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
|
ADC_ZPG: { exec_sum(); };
|
ADC_ZPG: { exec_sum(); };
|
ADC_ZPX: { exec_sum(); };
|
ADC_ZPX: { exec_sum(); };
|
ADC_ABS: { exec_sum(); };
|
ADC_ABS: { exec_sum(); };
|
ADC_ABX: { exec_sum(); };
|
ADC_ABX: { exec_sum(); };
|
| Line 255... |
Line 346... |
PLP_IMP: {
|
PLP_IMP: {
|
reg_status = inst.alu_a;
|
reg_status = inst.alu_a;
|
reg_status[5:5] = 1; // this is always one
|
reg_status[5:5] = 1; // this is always one
|
};
|
};
|
|
|
ROL_ACC: { exec_rot(TRUE, reg_a); };
|
ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
|
ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
|
ROR_ACC: { exec_rot(FALSE, reg_a); };
|
ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
|
ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
|
|
|
| Line 301... |
Line 392... |
TAX_IMP: { exec_transfer(reg_a, reg_x); };
|
TAX_IMP: { exec_transfer(reg_a, reg_x); };
|
TAY_IMP: { exec_transfer(reg_a, reg_y); };
|
TAY_IMP: { exec_transfer(reg_a, reg_y); };
|
TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
|
TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
|
TXA_IMP: { exec_transfer(reg_x, reg_a); };
|
TXA_IMP: { exec_transfer(reg_x, reg_a); };
|
TXS_IMP: { };
|
TXS_IMP: { };
|
TYA_IMP: { exec_transfer(reg_y, reg_a); reg_result = reg_y; }; // A = Y
|
TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
|
|
|
|
// note: tya and txa do not update the result register
|
|
|
default: {
|
default: {
|
// all the random generated opcodes will fall here
|
// all the random generated opcodes will fall here
|
}
|
}
|
};
|
};
|
| Line 320... |
Line 413... |
exec_sub() is {
|
exec_sub() is {
|
if (reg_status[3:3] == 1) {
|
if (reg_status[3:3] == 1) {
|
var op1 : int;
|
var op1 : int;
|
var op2 : int;
|
var op2 : int;
|
|
|
|
warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
|
|
|
//out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
//out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
|
|
op1 = inst.alu_a[3:0];
|
op1 = inst.alu_a[3:0];
|
op2 = inst.alu_a[7:4];
|
op2 = inst.alu_a[7:4];
|
|
|
| Line 368... |
Line 463... |
|
|
reg_a = reg_result;
|
reg_a = reg_result;
|
|
|
};
|
};
|
|
|
exec_rot(left : bool, arg1 : *byte) is {
|
exec_rot(left : bool, arg1 : byte) is {
|
var oldcarry : bit;
|
var oldcarry : bit;
|
|
|
if (left) {
|
if (left) {
|
oldcarry = reg_status[0:0];
|
oldcarry = reg_status[0:0];
|
reg_status[0:0] = arg1[7:7];
|
reg_status[0:0] = arg1[7:7];
|
arg1 = arg1 << 1;
|
reg_result = arg1 << 1;
|
arg1[0:0] = oldcarry;
|
reg_result[0:0] = oldcarry;
|
}
|
}
|
else {
|
else {
|
oldcarry = reg_status[0:0];
|
oldcarry = reg_status[0:0];
|
reg_status[0:0] = arg1[0:0];
|
reg_status[0:0] = arg1[0:0];
|
arg1 = arg1 >> 1;
|
reg_result = arg1 >> 1;
|
arg1[7:7] = oldcarry;
|
reg_result[7:7] = oldcarry;
|
};
|
};
|
|
|
reg_result = arg1;
|
update_z(reg_result);
|
update_z(arg1);
|
update_n(reg_result);
|
update_n(arg1);
|
|
};
|
};
|
|
|
exec_or() is {
|
exec_or() is {
|
reg_a = reg_a | inst.alu_a;
|
reg_a = reg_a | inst.alu_a;
|
reg_result = reg_a;
|
reg_result = reg_a;
|
