| Line 456... |
Line 456... |
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temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
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temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
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reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
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reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
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reg_status[7:7] = temp[7:7]; // N
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reg_status[7:7] = temp[7:7]; // N
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print (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
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//print (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
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reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
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reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
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if (reg_result == 0) {
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if (reg_result == 0) {
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reg_status[1:1] = 1; // Z
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reg_status[1:1] = 1; // Z
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} else {
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} else {
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reg_status[1:1] = 0; // Z
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reg_status[1:1] = 0; // Z
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};
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};
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reg_a = temp.as_a(byte);
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reg_a = temp.as_a(byte);
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print (temp & 0xff00);
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//print (temp & 0xff00);
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print (temp & 0xff00) != 0x0000;
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//print (temp & 0xff00) != 0x0000;
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if ( (temp & 0xff00) != 0x0000 ) {
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if ( (temp & 0xff00) != 0x0000 ) {
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reg_status[0:0] = 0;
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reg_status[0:0] = 0;
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} else {
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} else {
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reg_status[0:0] = 1;
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reg_status[0:0] = 1;
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| Line 596... |
Line 596... |
exec_sum() is {
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exec_sum() is {
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//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
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//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
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if (reg_status[3:3] == 1) {
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if (reg_status[3:3] == 1) {
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var op1 : byte;
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var op1 : byte;
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var op2 : byte;
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var op2 : byte;
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var aux : byte;
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//out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
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//out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
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op1 = inst.alu_a[3:0];
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op1 = reg_a[3:0] + inst.alu_a[3:0] + reg_status[0:0];
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op2 = inst.alu_a[7:4];
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print op1;
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//Int32 lo = (A & 0x0f) + (operand & 0x0f) + (C ? 1 : 0);
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op2 = reg_a[7:4] + inst.alu_a[7:4];
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//carry_aux = reg_a[7:4] + inst.alu_a[7:4];
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print op2;
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//Int32 hi = (A & 0xf0) + (operand & 0xf0);
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op1 = reg_a[3:0] + op1 + reg_status[0:0];
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aux = op1 + op2;
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op2 = reg_a[7:4] + op2;
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if (op1 >= 10) {
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if (aux[7:0] == 0) {
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op2 = op2 + op1/ 10;
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reg_status[1:1] = 1;
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op1 = op1 % 10;
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};
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if (op2 >= 10) {
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op2 = op2 % 10;
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reg_status[0:0] = 1;
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}
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}
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else {
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else {
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reg_status[0:0] = 0;
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reg_status[1:1] = 0;
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};
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};
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//notZ = (lo+hi) & 0xff;
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reg_result[3:0] = op1;
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if (op1 > 0x09) {
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reg_result[7:4] = op2;
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op2 += 0x01;
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update_z(reg_result);
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op1 += 0x06;
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update_n(reg_result);
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};
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update_v(reg_a, inst.alu_a, reg_result);
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reg_a = reg_result;
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reg_status[7:7] = op2[3:3];
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//N = hi & 0x80;
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reg_status[6:6] = ~(reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ op2[3:3]); // V
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//V = ~(A ^ operand) & (A ^ hi) & 0x80;
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print op2;
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if (op2 > 0x09) {
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op2 += 0x06;
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print op2;
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};
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//if (hi > 0x90) hi += 0x60;
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reg_status[0:0] = (op2 > 15) ? 1 : 0;
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//C = hi & 0xff00;
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reg_a[3:0] = op1[3:0];
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reg_a[7:4] = op2[3:0];
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//reg_a = (lo & 0x0f) + (hi & 0xf0);
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reg_result = reg_a;
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}
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}
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else { // stella checked
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else { // stella checked
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reg_result = reg_a + inst.alu_a + reg_status[0:0];
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reg_result = reg_a + inst.alu_a + reg_status[0:0];
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update_n(reg_result);
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update_n(reg_result);
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update_v(reg_a, inst.alu_a, reg_result);
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update_v(reg_a, inst.alu_a, reg_result);
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