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[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Diff between revs 234 and 235

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Rev 234 Rev 235
Line 78... Line 78...
 
 
                        case inst.input_kind {
                        case inst.input_kind {
                                ENABLED_VALID: {
                                ENABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        execute(inst.alu_opcode);
                                        execute(inst.alu_opcode);
 
 
                                        if (reg_status[3:3] == 1) {
 
                                                case inst.alu_opcode {
 
                                                        SBC_IMM: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                        SBC_ZPG: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                        SBC_ZPX: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                        SBC_ABS: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                        SBC_ABX: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                        SBC_ABY: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                        SBC_IDX: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                        SBC_IDY: {
 
                                                                reg_a = alu_result;
 
                                                                reg_result = alu_result;
 
                                                                reg_status = alu_status;
 
                                                        };
 
                                                };
 
                                        };
 
                                };
                                };
                                RESET: {
                                RESET: {
                                        reg_x = 0;
                                        reg_x = 0;
                                        reg_y = 0;
                                        reg_y = 0;
                                        reg_status = 8'b00100010;
                                        reg_status = 8'b00100010;
                                        reg_a = 0; // TODO: check this
                                        reg_a = 0;
                                        reg_result = 0;
                                        reg_result = 0;
 
 
                                        return;
                                        return;
                                };
                                };
                                ENABLED_RAND: {
                                ENABLED_RAND: {
Line 409... Line 364...
                update_z(dest);
                update_z(dest);
                update_n(dest);
                update_n(dest);
        };
        };
 
 
        exec_sub() is {
        exec_sub() is {
                if (reg_status[3:3] == 1) { // decimal
 
                        var op1 : int;
 
                        var op2 : int;
 
 
 
                        warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
 
 
 
                        //out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
 
 
 
                        op1 = inst.alu_a[3:0];
 
                        op2 = inst.alu_a[7:4];
 
 
 
                        op1 = reg_a[3:0] - op1 -1 + reg_status[0:0];
 
                        op2 = reg_a[7:4] - op2;
 
 
 
                        if (op1 >= 10) {
 
                                op2 = op2  + op1/10;
 
                                op1 = op1 % 10;
 
                        } else if (op1 < 0) {
 
                                op2 = op2 - op1/10;
 
                                op1 = -(op1 % 10);
 
                        };
 
 
 
                        reg_status[0:0] = 1;
 
 
 
                        if (op2 >= 10) {
 
                                op2 = op2 % 10;
 
                        }
 
                        else if (op2 < 0) {
 
                                op2 = op2 + 10;
 
                                reg_status[0:0] = 0;
 
                        };
 
 
 
                        reg_result[3:0] = op1;
 
                        reg_result[7:4] = op2;
 
 
 
                        update_n(reg_result);
 
                        update_z(reg_result);
 
                        update_v(reg_a, inst.alu_a, reg_result);
 
                        reg_a = reg_result;
 
                }
 
                else {
 
                        var temp: int;
                        var temp: int;
 
 
                        temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
                        temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
                        reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
                        reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
 
 
                        reg_status[7:7] = temp[7:7]; // N
                        reg_status[7:7] = temp[7:7]; // N
                        //print  (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
                        //print  (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
                        reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
                        reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
 
 
 
                print reg_result;
                        if (reg_result == 0) {
                        if (reg_result == 0) {
                                reg_status[1:1] = 1; // Z
                                reg_status[1:1] = 1; // Z
                        } else {
                        } else {
                                reg_status[1:1] = 0; // Z
                                reg_status[1:1] = 0; // Z
                        };
                        };
 
 
                        reg_a = temp.as_a(byte);
                if (reg_status[3:3] == 1) { // decimal
 
                        var op1 : int;
 
                        var op2 : int;
 
 
 
                        op1 = (reg_a & 0x0f ) - (inst.alu_a & 0x0f) - ( (reg_status[0:0] == 1) ? 0 : 1);
 
                        print op1;
 
                        op2 = (reg_a & 0xf0) - (inst.alu_a & 0xf0);
 
                        print op2;
 
 
 
                        if (op1[4:4] == 1) {
 
                                op1 -= 6;
 
                                op2 = op2 - 1;
 
                        };
 
                        print op1;
 
                        print op2;
 
 
 
                        if(op2[8:8] == 1) {
 
                              op2 -= 0x60;
 
                        };
 
                        print op2;
 
 
                        //print  (temp & 0xff00);
                        reg_a = (op1 & 0x0f) | (op2 & 0xf0);
                        //print (temp & 0xff00) != 0x0000;
                        reg_result = reg_a;
 
                }
 
                else {
 
                        reg_a = temp.as_a(byte);
 
                };
 
 
                        if ( (temp & 0xff00) != 0x0000 ) {
                        if ( (temp & 0xff00) != 0x0000 ) {
                                reg_status[0:0] = 0;
                                reg_status[0:0] = 0;
                        } else {
                        } else {
                                reg_status[0:0] = 1;
                                reg_status[0:0] = 1;
                        }
 
 
 
                };
                };
        };
        };
 
 
        exec_rot(left : bool, arg1 : byte) is {
        exec_rot(left : bool, arg1 : byte) is {
                var oldcarry : bit;
                var oldcarry : bit;
Line 598... Line 534...
                if (reg_status[3:3] == 1) {
                if (reg_status[3:3] == 1) {
                        var op1 : byte;
                        var op1 : byte;
                        var op2 : byte;
                        var op2 : byte;
                        var aux : byte;
                        var aux : byte;
 
 
                        //out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
 
 
 
                        op1 = reg_a[3:0] + inst.alu_a[3:0] + reg_status[0:0];
                        op1 = reg_a[3:0] + inst.alu_a[3:0] + reg_status[0:0];
                        print op1;
 
                        //Int32 lo = (A & 0x0f) + (operand & 0x0f) + (C ? 1 : 0);
                        //Int32 lo = (A & 0x0f) + (operand & 0x0f) + (C ? 1 : 0);
 
 
                        op2 = reg_a[7:4] + inst.alu_a[7:4];
                        op2 = reg_a[7:4] + inst.alu_a[7:4];
                        //carry_aux = reg_a[7:4] + inst.alu_a[7:4];
                        //carry_aux = reg_a[7:4] + inst.alu_a[7:4];
                        print op2;
 
                        //Int32 hi = (A & 0xf0) + (operand & 0xf0);
                        //Int32 hi = (A & 0xf0) + (operand & 0xf0);
 
 
                        aux = op1 + op2;
                        aux = op1 + op2;
 
 
                        if (aux[7:0] == 0) {
                        if (aux[7:0] == 0) {
Line 629... Line 561...
                        reg_status[7:7] = op2[3:3];
                        reg_status[7:7] = op2[3:3];
                        //N = hi & 0x80;
                        //N = hi & 0x80;
 
 
                        reg_status[6:6] = ~(reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ op2[3:3]); // V
                        reg_status[6:6] = ~(reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ op2[3:3]); // V
                        //V = ~(A ^ operand) & (A ^ hi) & 0x80;
                        //V = ~(A ^ operand) & (A ^ hi) & 0x80;
                        print op2;
 
                        if (op2 > 0x09) {
                        if (op2 > 0x09) {
                                op2 += 0x06;
                                op2 += 0x06;
                                print op2;
 
                        };
                        };
                        //if (hi > 0x90) hi += 0x60;
                        //if (hi > 0x90) hi += 0x60;
 
 
                        reg_status[0:0] = (op2 > 15) ? 1 : 0;
                        reg_status[0:0] = (op2 > 15) ? 1 : 0;
                        //C = hi & 0xff00;
                        //C = hi & 0xff00;

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