| Line 185... |
Line 185... |
ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
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ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
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ASL_ZPX: { exec_asl_mem(); };
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ASL_ZPX: { exec_asl_mem(); };
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ASL_ABS: { exec_asl_mem(); };
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ASL_ABS: { exec_asl_mem(); };
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ASL_ABX: { exec_asl_mem(); };
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ASL_ABX: { exec_asl_mem(); };
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BCC_REL: {}; // nothing is done. these are all branches.
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//BCC_REL: {}; // nothing is done. these are all branches.
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BCS_REL: {};
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//BCS_REL: {};
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BEQ_REL: {};
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//BEQ_REL: {};
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BMI_REL: {};
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//BMI_REL: {};
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BNE_REL: {};
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//BNE_REL: {};
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BPL_REL: {};
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//BPL_REL: {};
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BVC_REL: {};
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//BVC_REL: {};
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BVS_REL: {};
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//BVS_REL: {};
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BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
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BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
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BIT_ABS: { exec_bit(); };
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BIT_ABS: { exec_bit(); };
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BRK_IMP: { reg_status[4:4] = 1; };
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BRK_IMP: { reg_status[4:4] = 1; };
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| Line 246... |
Line 246... |
INC_ABX: { exec_inc(inst.alu_a, TRUE); };
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INC_ABX: { exec_inc(inst.alu_a, TRUE); };
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INX_IMP: { exec_inc(reg_x, FALSE); };
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INX_IMP: { exec_inc(reg_x, FALSE); };
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INY_IMP: { exec_inc(reg_y, FALSE); };
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INY_IMP: { exec_inc(reg_y, FALSE); };
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JMP_ABS: {};
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//JMP_ABS: {};
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JMP_IND: {};
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//JMP_IND: {};
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JSR_ABS: {};
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//JSR_ABS: {};
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LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
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LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
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LDA_ZPG: { exec_load(reg_a, TRUE); };
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LDA_ZPG: { exec_load(reg_a, TRUE); };
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LDA_ZPX: { exec_load(reg_a, TRUE); };
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LDA_ZPX: { exec_load(reg_a, TRUE); };
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LDA_ABS: { exec_load(reg_a, TRUE); };
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LDA_ABS: { exec_load(reg_a, TRUE); };
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| Line 277... |
Line 277... |
LSR_ZPG: { exec_lsr(inst.alu_a); };
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LSR_ZPG: { exec_lsr(inst.alu_a); };
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LSR_ZPX: { exec_lsr(inst.alu_a); };
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LSR_ZPX: { exec_lsr(inst.alu_a); };
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LSR_ABS: { exec_lsr(inst.alu_a); };
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LSR_ABS: { exec_lsr(inst.alu_a); };
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LSR_ABX: { exec_lsr(inst.alu_a); };
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LSR_ABX: { exec_lsr(inst.alu_a); };
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NOP_IMP: {};
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//NOP_IMP: {};
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ORA_IMM: { exec_or(); }; // A,Z,N = A|M
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ORA_IMM: { exec_or(); }; // A,Z,N = A|M
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ORA_ZPG: { exec_or(); };
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ORA_ZPG: { exec_or(); };
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ORA_ZPX: { exec_or(); };
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ORA_ZPX: { exec_or(); };
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ORA_ABS: { exec_or(); };
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ORA_ABS: { exec_or(); };
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| Line 289... |
Line 289... |
ORA_ABY: { exec_or(); };
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ORA_ABY: { exec_or(); };
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ORA_IDX: { exec_or(); };
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ORA_IDX: { exec_or(); };
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ORA_IDY: { exec_or(); };
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ORA_IDY: { exec_or(); };
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PHA_IMP: { reg_result = reg_a; };
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PHA_IMP: { reg_result = reg_a; };
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PHP_IMP: {}; // P is always connected and the result is not updated
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//PHP_IMP: {}; // P is always connected and the result is not updated
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PLA_IMP: {
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PLA_IMP: {
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reg_a = inst.alu_a;
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reg_a = inst.alu_a;
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reg_result = inst.alu_a;
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reg_result = inst.alu_a;
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update_z(reg_a);
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update_z(reg_a);
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update_n(reg_a);
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update_n(reg_a);
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| Line 313... |
Line 313... |
ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
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ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
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ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
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ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
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ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
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ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
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RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
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RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
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RTS_IMP: { };
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//RTS_IMP: { };
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SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
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SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
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SBC_ZPG: { exec_sub(); };
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SBC_ZPG: { exec_sub(); };
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SBC_ZPX: { exec_sub(); };
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SBC_ZPX: { exec_sub(); };
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SBC_ABS: { exec_sub(); };
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SBC_ABS: { exec_sub(); };
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| Line 370... |
Line 370... |
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temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
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temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
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reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
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reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
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|
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reg_status[7:7] = temp[7:7]; // N
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reg_status[7:7] = temp[7:7]; // N
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//print (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
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reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
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reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
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|
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print reg_result;
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if (reg_result == 0) {
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if (reg_result == 0) {
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reg_status[1:1] = 1; // Z
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reg_status[1:1] = 1; // Z
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} else {
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} else {
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reg_status[1:1] = 0; // Z
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reg_status[1:1] = 0; // Z
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};
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};
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| Line 385... |
Line 383... |
if (reg_status[3:3] == 1) { // decimal
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if (reg_status[3:3] == 1) { // decimal
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var op1 : int;
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var op1 : int;
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var op2 : int;
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var op2 : int;
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|
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op1 = (reg_a & 0x0f ) - (inst.alu_a & 0x0f) - ( (reg_status[0:0] == 1) ? 0 : 1);
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op1 = (reg_a & 0x0f ) - (inst.alu_a & 0x0f) - ( (reg_status[0:0] == 1) ? 0 : 1);
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print op1;
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op2 = (reg_a & 0xf0) - (inst.alu_a & 0xf0);
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op2 = (reg_a & 0xf0) - (inst.alu_a & 0xf0);
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print op2;
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|
|
|
if (op1[4:4] == 1) {
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if (op1[4:4] == 1) {
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op1 -= 6;
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op1 -= 6;
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op2 = op2 - 1;
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op2 = op2 - 1;
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};
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};
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print op1;
|
|
print op2;
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|
|
if(op2[8:8] == 1) {
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if(op2[8:8] == 1) {
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op2 -= 0x60;
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op2 -= 0x60;
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};
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};
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print op2;
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|
|
|
reg_a = (op1 & 0x0f) | (op2 & 0xf0);
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reg_a = (op1 & 0x0f) | (op2 & 0xf0);
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reg_result = reg_a;
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reg_result = reg_a;
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}
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}
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else {
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else {
|
