| Line 258... |
Line 258... |
instruction == ORA_IDX ||
|
instruction == ORA_IDX ||
|
instruction == EOR_IDX ||
|
instruction == EOR_IDX ||
|
instruction == AND_IDX ||
|
instruction == AND_IDX ||
|
instruction == ADC_IDX ||
|
instruction == ADC_IDX ||
|
instruction == CMP_IDX ||
|
instruction == CMP_IDX ||
|
instruction == SBC_IDX
|
instruction == SBC_IDX ||
|
|
instruction == LDA_IDY ||
|
|
--instruction == STA_IDY ||
|
|
instruction == ORA_IDY ||
|
|
instruction == EOR_IDY ||
|
|
instruction == AND_IDY ||
|
|
instruction == ADC_IDY ||
|
|
instruction == CMP_IDY ||
|
|
instruction == SBC_IDY
|
) : {
|
) : {
|
new_state = CYCLE_3;
|
new_state = CYCLE_3;
|
pointer = input.data_in;
|
pointer = input.data_in;
|
};
|
};
|
(
|
(
|
| Line 322... |
Line 330... |
instruction == SBC_IDX
|
instruction == SBC_IDX
|
) : {
|
) : {
|
new_state = CYCLE_4;
|
new_state = CYCLE_4;
|
};
|
};
|
(
|
(
|
|
instruction == LDA_IDY ||
|
|
--instruction == STA_IDY ||
|
|
instruction == ORA_IDY ||
|
|
instruction == EOR_IDY ||
|
|
instruction == AND_IDY ||
|
|
instruction == ADC_IDY ||
|
|
instruction == CMP_IDY ||
|
|
instruction == SBC_IDY
|
|
) : {
|
|
new_state = CYCLE_4;
|
|
PCL = input.data_in;
|
|
};
|
|
(
|
instruction == ADC_ABS ||
|
instruction == ADC_ABS ||
|
instruction == ASL_ABS ||
|
instruction == ASL_ABS ||
|
instruction == BIT_ABS ||
|
instruction == BIT_ABS ||
|
instruction == AND_ABS ||
|
instruction == AND_ABS ||
|
instruction == CMP_ABS ||
|
instruction == CMP_ABS ||
|
| Line 453... |
Line 474... |
instruction == SBC_IDX
|
instruction == SBC_IDX
|
) : {
|
) : {
|
new_state = CYCLE_5;
|
new_state = CYCLE_5;
|
PCL = input.data_in;
|
PCL = input.data_in;
|
};
|
};
|
|
(
|
|
instruction == LDA_IDY ||
|
|
--instruction == STA_IDY ||
|
|
instruction == ORA_IDY ||
|
|
instruction == EOR_IDY ||
|
|
instruction == AND_IDY ||
|
|
instruction == ADC_IDY ||
|
|
instruction == CMP_IDY ||
|
|
instruction == SBC_IDY
|
|
) : {
|
|
new_state = CYCLE_5;
|
|
PCH = input.data_in;
|
|
};
|
default : {
|
default : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
};
|
};
|
};
|
};
|
};
|
};
|
| Line 494... |
Line 528... |
instruction == ASL_ABX ||
|
instruction == ASL_ABX ||
|
instruction == LSR_ABX ||
|
instruction == LSR_ABX ||
|
instruction == ROL_ABX ||
|
instruction == ROL_ABX ||
|
instruction == ROR_ABX ||
|
instruction == ROR_ABX ||
|
instruction == INC_ABX ||
|
instruction == INC_ABX ||
|
instruction == DEC_ABX
|
instruction == DEC_ABX ||
|
|
(
|
|
more_cycles == TRUE &&
|
|
(
|
|
instruction == LDA_IDY ||
|
|
--instruction == STA_IDY ||
|
|
instruction == ORA_IDY ||
|
|
instruction == EOR_IDY ||
|
|
instruction == AND_IDY ||
|
|
instruction == ADC_IDY ||
|
|
instruction == CMP_IDY ||
|
|
instruction == SBC_IDY
|
|
)
|
|
)
|
) : {
|
) : {
|
new_state = CYCLE_6;
|
new_state = CYCLE_6;
|
};
|
};
|
(
|
(
|
instruction == LDA_IDX ||
|
instruction == LDA_IDX ||
|
| Line 645... |
Line 692... |
last_instruction == ORA_IDX ||
|
last_instruction == ORA_IDX ||
|
last_instruction == EOR_IDX ||
|
last_instruction == EOR_IDX ||
|
last_instruction == AND_IDX ||
|
last_instruction == AND_IDX ||
|
last_instruction == ADC_IDX ||
|
last_instruction == ADC_IDX ||
|
last_instruction == CMP_IDX ||
|
last_instruction == CMP_IDX ||
|
last_instruction == SBC_IDX
|
last_instruction == SBC_IDX ||
|
|
last_instruction == LDA_IDY ||
|
|
last_instruction == ORA_IDY ||
|
|
last_instruction == EOR_IDY ||
|
|
last_instruction == AND_IDY ||
|
|
last_instruction == ADC_IDY ||
|
|
last_instruction == CMP_IDY ||
|
|
last_instruction == SBC_IDY
|
) : {
|
) : {
|
if (alu_opcode != last_instruction) {
|
if (alu_opcode != last_instruction) {
|
dut_error("alu_opcode is Wrong!");
|
dut_error("alu_opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 1) {
|
if (alu_enable != 1) {
|
| Line 808... |
Line 862... |
instructions == ORA_IDX ||
|
instructions == ORA_IDX ||
|
instructions == EOR_IDX ||
|
instructions == EOR_IDX ||
|
instructions == AND_IDX ||
|
instructions == AND_IDX ||
|
instructions == ADC_IDX ||
|
instructions == ADC_IDX ||
|
instructions == CMP_IDX ||
|
instructions == CMP_IDX ||
|
instructions == SBC_IDX
|
instructions == SBC_IDX ||
|
|
instructions == LDA_IDY ||
|
|
--instructions == STA_IDY ||
|
|
instructions == ORA_IDY ||
|
|
instructions == EOR_IDY ||
|
|
instructions == AND_IDY ||
|
|
instructions == ADC_IDY ||
|
|
instructions == CMP_IDY ||
|
|
instructions == SBC_IDY
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 1051... |
Line 1113... |
instructions == ORA_IDX ||
|
instructions == ORA_IDX ||
|
instructions == EOR_IDX ||
|
instructions == EOR_IDX ||
|
instructions == AND_IDX ||
|
instructions == AND_IDX ||
|
instructions == ADC_IDX ||
|
instructions == ADC_IDX ||
|
instructions == CMP_IDX ||
|
instructions == CMP_IDX ||
|
instructions == SBC_IDX
|
instructions == SBC_IDX ||
|
|
instructions == LDA_IDY ||
|
|
--instructions == STA_IDY ||
|
|
instructions == ORA_IDY ||
|
|
instructions == EOR_IDY ||
|
|
instructions == AND_IDY ||
|
|
instructions == ADC_IDY ||
|
|
instructions == CMP_IDY ||
|
|
instructions == SBC_IDY
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 1366... |
Line 1436... |
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == LDA_IDY ||
|
|
--instructions == STA_IDY ||
|
|
instructions == ORA_IDY ||
|
|
instructions == EOR_IDY ||
|
|
instructions == AND_IDY ||
|
|
instructions == ADC_IDY ||
|
|
instructions == CMP_IDY ||
|
|
instructions == SBC_IDY
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr != pointer + 1) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (PCL + Y > 255) {
|
|
more_cycles = TRUE;
|
|
};
|
|
};
|
|
(
|
instructions == LDX_ZPY ||
|
instructions == LDX_ZPY ||
|
instructions == LDA_ABY ||
|
instructions == LDA_ABY ||
|
instructions == LDX_ABY ||
|
instructions == LDX_ABY ||
|
instructions == EOR_ABY ||
|
instructions == EOR_ABY ||
|
instructions == AND_ABY ||
|
instructions == AND_ABY ||
|
| Line 1612... |
Line 1708... |
// };
|
// };
|
// SP = SP - 1;
|
// SP = SP - 1;
|
//};
|
//};
|
(
|
(
|
instructions == LDA_IDX ||
|
instructions == LDA_IDX ||
|
instructions == STA_IDX ||
|
|
instructions == ORA_IDX ||
|
instructions == ORA_IDX ||
|
instructions == EOR_IDX ||
|
instructions == EOR_IDX ||
|
instructions == AND_IDX ||
|
instructions == AND_IDX ||
|
instructions == ADC_IDX ||
|
instructions == ADC_IDX ||
|
instructions == CMP_IDX ||
|
instructions == CMP_IDX ||
|
| Line 1641... |
Line 1736... |
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == LDA_IDY ||
|
|
--instructions == STA_IDY ||
|
|
instructions == ORA_IDY ||
|
|
instructions == EOR_IDY ||
|
|
instructions == AND_IDY ||
|
|
instructions == ADC_IDY ||
|
|
instructions == CMP_IDY ||
|
|
instructions == SBC_IDY
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (PCL + Y > 255) {
|
|
if (addr[7:0] != PCL + Y - 256) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + Y) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
};
|
|
(
|
|
instructions == STA_IDX
|
|
) : {
|
|
if (alu_opcode != instructions) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 1) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (pointer + X + 1 > 255) {
|
|
if (addr[7:0] != pointer + X + 1 - 256) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != pointer + X + 1) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
};
|
|
(
|
instructions == RTI_IMP
|
instructions == RTI_IMP
|
) : {
|
) : {
|
if (alu_opcode != instructions) {
|
if (alu_opcode != instructions) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
| Line 1898... |
Line 2046... |
if (addr[12:8] != PCH[4:0]) {
|
if (addr[12:8] != PCH[4:0]) {
|
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
(
|
(
|
instructions == STA_IDX ||
|
instructions == LDA_IDY ||
|
|
--instructions == STA_IDY ||
|
|
instructions == ORA_IDY ||
|
|
instructions == EOR_IDY ||
|
|
instructions == AND_IDY ||
|
|
instructions == ADC_IDY ||
|
|
instructions == CMP_IDY ||
|
|
instructions == SBC_IDY
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL + Y - 256) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
if (addr[12:8] != PCH[4:0] + 1) {
|
|
print PCH, addr[12:8];
|
|
print PCL + Y, addr[7:0];
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
(
|
|
instructions == STA_IDX
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
