| Line 14... |
Line 14... |
// keep soft SP == 9'b100000000;
|
// keep soft SP == 9'b100000000;
|
!SP : byte;
|
!SP : byte;
|
keep soft SP == 0;
|
keep soft SP == 0;
|
!pointer : byte;
|
!pointer : byte;
|
keep soft pointer == 0;
|
keep soft pointer == 0;
|
|
!pointer_h : byte;
|
|
keep soft pointer_h == 0;
|
|
|
!more_cycles : bool;
|
!more_cycles : bool;
|
keep soft more_cycles == FALSE;
|
keep soft more_cycles == FALSE;
|
--!R : byte;
|
--!R : byte;
|
-- keep soft R == 0;
|
-- keep soft R == 0;
|
| Line 172... |
Line 174... |
instruction == ADC_ABS ||
|
instruction == ADC_ABS ||
|
instruction == ASL_ABS ||
|
instruction == ASL_ABS ||
|
instruction == BIT_ABS ||
|
instruction == BIT_ABS ||
|
instruction == AND_ABS ||
|
instruction == AND_ABS ||
|
instruction == CMP_ABS ||
|
instruction == CMP_ABS ||
|
|
instruction == CPX_ABS ||
|
|
instruction == CPY_ABS ||
|
instruction == DEC_ABS ||
|
instruction == DEC_ABS ||
|
instruction == EOR_ABS ||
|
instruction == EOR_ABS ||
|
instruction == INC_ABS ||
|
instruction == INC_ABS ||
|
instruction == JMP_ABS ||
|
instruction == JMP_ABS ||
|
instruction == LDA_ABS ||
|
instruction == LDA_ABS ||
|
| Line 196... |
Line 200... |
instruction == AND_ZPG ||
|
instruction == AND_ZPG ||
|
instruction == ORA_ZPG ||
|
instruction == ORA_ZPG ||
|
instruction == ADC_ZPG ||
|
instruction == ADC_ZPG ||
|
instruction == SBC_ZPG ||
|
instruction == SBC_ZPG ||
|
instruction == CMP_ZPG ||
|
instruction == CMP_ZPG ||
|
|
instruction == CPX_ZPG ||
|
|
instruction == CPY_ZPG ||
|
instruction == BIT_ZPG ||
|
instruction == BIT_ZPG ||
|
instruction == STA_ZPG ||
|
instruction == STA_ZPG ||
|
instruction == STX_ZPG ||
|
instruction == STX_ZPG ||
|
instruction == STY_ZPG ||
|
instruction == STY_ZPG ||
|
instruction == ASL_ZPG ||
|
instruction == ASL_ZPG ||
|
| Line 226... |
Line 232... |
instruction == STA_ZPX ||
|
instruction == STA_ZPX ||
|
instruction == STX_ZPY ||
|
instruction == STX_ZPY ||
|
instruction == STY_ZPX ||
|
instruction == STY_ZPX ||
|
instruction == LDA_ABX ||
|
instruction == LDA_ABX ||
|
instruction == LDA_ABY ||
|
instruction == LDA_ABY ||
|
|
instruction == STA_ABX ||
|
|
instruction == STA_ABY ||
|
instruction == LDX_ABY ||
|
instruction == LDX_ABY ||
|
instruction == LDY_ABX ||
|
instruction == LDY_ABX ||
|
instruction == EOR_ABX ||
|
instruction == EOR_ABX ||
|
instruction == EOR_ABY ||
|
instruction == EOR_ABY ||
|
instruction == AND_ABX ||
|
instruction == AND_ABX ||
|
| Line 260... |
Line 268... |
instruction == AND_IDX ||
|
instruction == AND_IDX ||
|
instruction == ADC_IDX ||
|
instruction == ADC_IDX ||
|
instruction == CMP_IDX ||
|
instruction == CMP_IDX ||
|
instruction == SBC_IDX ||
|
instruction == SBC_IDX ||
|
instruction == LDA_IDY ||
|
instruction == LDA_IDY ||
|
--instruction == STA_IDY ||
|
instruction == STA_IDY ||
|
instruction == ORA_IDY ||
|
instruction == ORA_IDY ||
|
instruction == EOR_IDY ||
|
instruction == EOR_IDY ||
|
instruction == AND_IDY ||
|
instruction == AND_IDY ||
|
instruction == ADC_IDY ||
|
instruction == ADC_IDY ||
|
instruction == CMP_IDY ||
|
instruction == CMP_IDY ||
|
instruction == SBC_IDY
|
instruction == SBC_IDY ||
|
|
instruction == JMP_IND
|
) : {
|
) : {
|
new_state = CYCLE_3;
|
new_state = CYCLE_3;
|
pointer = input.data_in;
|
pointer = input.data_in;
|
};
|
};
|
(
|
(
|
| Line 331... |
Line 340... |
) : {
|
) : {
|
new_state = CYCLE_4;
|
new_state = CYCLE_4;
|
};
|
};
|
(
|
(
|
instruction == LDA_IDY ||
|
instruction == LDA_IDY ||
|
--instruction == STA_IDY ||
|
instruction == STA_IDY ||
|
instruction == ORA_IDY ||
|
instruction == ORA_IDY ||
|
instruction == EOR_IDY ||
|
instruction == EOR_IDY ||
|
instruction == AND_IDY ||
|
instruction == AND_IDY ||
|
instruction == ADC_IDY ||
|
instruction == ADC_IDY ||
|
instruction == CMP_IDY ||
|
instruction == CMP_IDY ||
|
| Line 343... |
Line 352... |
) : {
|
) : {
|
new_state = CYCLE_4;
|
new_state = CYCLE_4;
|
PCL = input.data_in;
|
PCL = input.data_in;
|
};
|
};
|
(
|
(
|
|
instruction == JMP_IND
|
|
) : {
|
|
new_state = CYCLE_4;
|
|
pointer_h = input.data_in;
|
|
};
|
|
(
|
instruction == ADC_ABS ||
|
instruction == ADC_ABS ||
|
instruction == ASL_ABS ||
|
instruction == ASL_ABS ||
|
instruction == BIT_ABS ||
|
instruction == BIT_ABS ||
|
instruction == AND_ABS ||
|
instruction == AND_ABS ||
|
instruction == CMP_ABS ||
|
instruction == CMP_ABS ||
|
|
instruction == CPX_ABS ||
|
|
instruction == CPY_ABS ||
|
instruction == DEC_ABS ||
|
instruction == DEC_ABS ||
|
instruction == EOR_ABS ||
|
instruction == EOR_ABS ||
|
instruction == INC_ABS ||
|
instruction == INC_ABS ||
|
instruction == LDA_ABS ||
|
instruction == LDA_ABS ||
|
instruction == LDX_ABS ||
|
instruction == LDX_ABS ||
|
| Line 364... |
Line 381... |
instruction == STA_ABS ||
|
instruction == STA_ABS ||
|
instruction == STX_ABS ||
|
instruction == STX_ABS ||
|
instruction == STY_ABS ||
|
instruction == STY_ABS ||
|
instruction == LDA_ABX ||
|
instruction == LDA_ABX ||
|
instruction == LDA_ABY ||
|
instruction == LDA_ABY ||
|
|
instruction == STA_ABX ||
|
|
instruction == STA_ABY ||
|
instruction == LDX_ABY ||
|
instruction == LDX_ABY ||
|
instruction == LDY_ABX ||
|
instruction == LDY_ABX ||
|
instruction == EOR_ABX ||
|
instruction == EOR_ABX ||
|
instruction == EOR_ABY ||
|
instruction == EOR_ABY ||
|
instruction == AND_ABX ||
|
instruction == AND_ABX ||
|
| Line 405... |
Line 424... |
case {
|
case {
|
//JSR_ABS : {
|
//JSR_ABS : {
|
// new_state = CYCLE_5;
|
// new_state = CYCLE_5;
|
//};
|
//};
|
(
|
(
|
instruction == RTS_IMP
|
instruction == RTS_IMP ||
|
|
instruction == JMP_IND
|
) : {
|
) : {
|
new_state = CYCLE_5;
|
new_state = CYCLE_5;
|
PCL = input.data_in;
|
PCL = input.data_in;
|
};
|
};
|
(
|
(
|
| Line 437... |
Line 457... |
instruction == LSR_ABX ||
|
instruction == LSR_ABX ||
|
instruction == ROL_ABX ||
|
instruction == ROL_ABX ||
|
instruction == ROR_ABX ||
|
instruction == ROR_ABX ||
|
instruction == INC_ABX ||
|
instruction == INC_ABX ||
|
instruction == DEC_ABX ||
|
instruction == DEC_ABX ||
|
|
instruction == STA_ABX ||
|
|
instruction == STA_ABY ||
|
(
|
(
|
more_cycles == TRUE &&
|
more_cycles == TRUE &&
|
(
|
(
|
instruction == LDA_ABX ||
|
instruction == LDA_ABX ||
|
instruction == LDA_ABY ||
|
instruction == LDA_ABY ||
|
| Line 476... |
Line 498... |
new_state = CYCLE_5;
|
new_state = CYCLE_5;
|
PCL = input.data_in;
|
PCL = input.data_in;
|
};
|
};
|
(
|
(
|
instruction == LDA_IDY ||
|
instruction == LDA_IDY ||
|
--instruction == STA_IDY ||
|
instruction == STA_IDY ||
|
instruction == ORA_IDY ||
|
instruction == ORA_IDY ||
|
instruction == EOR_IDY ||
|
instruction == EOR_IDY ||
|
instruction == AND_IDY ||
|
instruction == AND_IDY ||
|
instruction == ADC_IDY ||
|
instruction == ADC_IDY ||
|
instruction == CMP_IDY ||
|
instruction == CMP_IDY ||
|
| Line 529... |
Line 551... |
instruction == LSR_ABX ||
|
instruction == LSR_ABX ||
|
instruction == ROL_ABX ||
|
instruction == ROL_ABX ||
|
instruction == ROR_ABX ||
|
instruction == ROR_ABX ||
|
instruction == INC_ABX ||
|
instruction == INC_ABX ||
|
instruction == DEC_ABX ||
|
instruction == DEC_ABX ||
|
|
instruction == STA_IDY ||
|
(
|
(
|
more_cycles == TRUE &&
|
more_cycles == TRUE &&
|
(
|
(
|
instruction == LDA_IDY ||
|
instruction == LDA_IDY ||
|
--instruction == STA_IDY ||
|
|
instruction == ORA_IDY ||
|
instruction == ORA_IDY ||
|
instruction == EOR_IDY ||
|
instruction == EOR_IDY ||
|
instruction == AND_IDY ||
|
instruction == AND_IDY ||
|
instruction == ADC_IDY ||
|
instruction == ADC_IDY ||
|
instruction == CMP_IDY ||
|
instruction == CMP_IDY ||
|
| Line 558... |
Line 580... |
instruction == SBC_IDX
|
instruction == SBC_IDX
|
) : {
|
) : {
|
new_state = CYCLE_6;
|
new_state = CYCLE_6;
|
PCH = input.data_in;
|
PCH = input.data_in;
|
};
|
};
|
|
(
|
|
instruction == JMP_IND
|
|
) : {
|
|
new_state = CYCLE_1;
|
|
PCH = input.data_in;
|
|
};
|
default : {
|
default : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
};
|
};
|
};
|
};
|
};
|
};
|
| Line 634... |
Line 662... |
last_instruction == ADC_IMM ||
|
last_instruction == ADC_IMM ||
|
last_instruction == AND_ABS ||
|
last_instruction == AND_ABS ||
|
last_instruction == AND_IMM ||
|
last_instruction == AND_IMM ||
|
last_instruction == BIT_ABS ||
|
last_instruction == BIT_ABS ||
|
last_instruction == CMP_ABS ||
|
last_instruction == CMP_ABS ||
|
|
last_instruction == CPX_ABS ||
|
|
last_instruction == CPY_ABS ||
|
last_instruction == CMP_IMM ||
|
last_instruction == CMP_IMM ||
|
last_instruction == CPX_IMM ||
|
last_instruction == CPX_IMM ||
|
last_instruction == CPY_IMM ||
|
last_instruction == CPY_IMM ||
|
last_instruction == EOR_ABS ||
|
last_instruction == EOR_ABS ||
|
last_instruction == EOR_IMM ||
|
last_instruction == EOR_IMM ||
|
| Line 660... |
Line 690... |
last_instruction == AND_ZPG ||
|
last_instruction == AND_ZPG ||
|
last_instruction == ORA_ZPG ||
|
last_instruction == ORA_ZPG ||
|
last_instruction == ADC_ZPG ||
|
last_instruction == ADC_ZPG ||
|
last_instruction == SBC_ZPG ||
|
last_instruction == SBC_ZPG ||
|
last_instruction == CMP_ZPG ||
|
last_instruction == CMP_ZPG ||
|
|
last_instruction == CPX_ZPG ||
|
|
last_instruction == CPY_ZPG ||
|
last_instruction == BIT_ZPG ||
|
last_instruction == BIT_ZPG ||
|
last_instruction == LDA_ZPX ||
|
last_instruction == LDA_ZPX ||
|
last_instruction == LDX_ZPY ||
|
last_instruction == LDX_ZPY ||
|
last_instruction == LDY_ZPX ||
|
last_instruction == LDY_ZPX ||
|
last_instruction == EOR_ZPX ||
|
last_instruction == EOR_ZPX ||
|
| Line 778... |
Line 810... |
instructions == AND_IMM ||
|
instructions == AND_IMM ||
|
instructions == ASL_ABS ||
|
instructions == ASL_ABS ||
|
instructions == BIT_ABS ||
|
instructions == BIT_ABS ||
|
instructions == BRK_IMP ||
|
instructions == BRK_IMP ||
|
instructions == CMP_ABS ||
|
instructions == CMP_ABS ||
|
|
instructions == CPX_ABS ||
|
|
instructions == CPY_ABS ||
|
instructions == CMP_IMM ||
|
instructions == CMP_IMM ||
|
instructions == CPX_IMM ||
|
instructions == CPX_IMM ||
|
instructions == CPY_IMM ||
|
instructions == CPY_IMM ||
|
instructions == DEC_ABS ||
|
instructions == DEC_ABS ||
|
instructions == EOR_ABS ||
|
instructions == EOR_ABS ||
|
| Line 808... |
Line 842... |
instructions == AND_ZPG ||
|
instructions == AND_ZPG ||
|
instructions == ORA_ZPG ||
|
instructions == ORA_ZPG ||
|
instructions == ADC_ZPG ||
|
instructions == ADC_ZPG ||
|
instructions == SBC_ZPG ||
|
instructions == SBC_ZPG ||
|
instructions == CMP_ZPG ||
|
instructions == CMP_ZPG ||
|
|
instructions == CPX_ZPG ||
|
|
instructions == CPY_ZPG ||
|
instructions == BIT_ZPG ||
|
instructions == BIT_ZPG ||
|
instructions == ASL_ZPG ||
|
instructions == ASL_ZPG ||
|
instructions == LSR_ZPG ||
|
instructions == LSR_ZPG ||
|
instructions == ROL_ZPG ||
|
instructions == ROL_ZPG ||
|
instructions == ROR_ZPG ||
|
instructions == ROR_ZPG ||
|
| Line 835... |
Line 871... |
instructions == STX_ZPY ||
|
instructions == STX_ZPY ||
|
instructions == STY_ZPX ||
|
instructions == STY_ZPX ||
|
instructions == STA_ZPX ||
|
instructions == STA_ZPX ||
|
instructions == LDA_ABX ||
|
instructions == LDA_ABX ||
|
instructions == LDA_ABY ||
|
instructions == LDA_ABY ||
|
|
instructions == STA_ABX ||
|
|
instructions == STA_ABY ||
|
instructions == LDX_ABY ||
|
instructions == LDX_ABY ||
|
instructions == LDY_ABX ||
|
instructions == LDY_ABX ||
|
instructions == EOR_ABX ||
|
instructions == EOR_ABX ||
|
instructions == EOR_ABY ||
|
instructions == EOR_ABY ||
|
instructions == AND_ABX ||
|
instructions == AND_ABX ||
|
| Line 864... |
Line 902... |
instructions == AND_IDX ||
|
instructions == AND_IDX ||
|
instructions == ADC_IDX ||
|
instructions == ADC_IDX ||
|
instructions == CMP_IDX ||
|
instructions == CMP_IDX ||
|
instructions == SBC_IDX ||
|
instructions == SBC_IDX ||
|
instructions == LDA_IDY ||
|
instructions == LDA_IDY ||
|
--instructions == STA_IDY ||
|
instructions == STA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == EOR_IDY ||
|
instructions == EOR_IDY ||
|
instructions == AND_IDY ||
|
instructions == AND_IDY ||
|
instructions == ADC_IDY ||
|
instructions == ADC_IDY ||
|
instructions == CMP_IDY ||
|
instructions == CMP_IDY ||
|
instructions == SBC_IDY
|
instructions == SBC_IDY ||
|
|
instructions == JMP_IND
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 1115... |
Line 1154... |
instructions == AND_IDX ||
|
instructions == AND_IDX ||
|
instructions == ADC_IDX ||
|
instructions == ADC_IDX ||
|
instructions == CMP_IDX ||
|
instructions == CMP_IDX ||
|
instructions == SBC_IDX ||
|
instructions == SBC_IDX ||
|
instructions == LDA_IDY ||
|
instructions == LDA_IDY ||
|
--instructions == STA_IDY ||
|
instructions == STA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == EOR_IDY ||
|
instructions == EOR_IDY ||
|
instructions == AND_IDY ||
|
instructions == AND_IDY ||
|
instructions == ADC_IDY ||
|
instructions == ADC_IDY ||
|
instructions == CMP_IDY ||
|
instructions == CMP_IDY ||
|
| Line 1142... |
Line 1181... |
instructions == ADC_ABS ||
|
instructions == ADC_ABS ||
|
instructions == AND_ABS ||
|
instructions == AND_ABS ||
|
instructions == ASL_ABS ||
|
instructions == ASL_ABS ||
|
instructions == BIT_ABS ||
|
instructions == BIT_ABS ||
|
instructions == CMP_ABS ||
|
instructions == CMP_ABS ||
|
|
instructions == CPX_ABS ||
|
|
instructions == CPY_ABS ||
|
instructions == DEC_ABS ||
|
instructions == DEC_ABS ||
|
instructions == EOR_ABS ||
|
instructions == EOR_ABS ||
|
instructions == INC_ABS ||
|
instructions == INC_ABS ||
|
instructions == LDA_ABS ||
|
instructions == LDA_ABS ||
|
instructions == LDX_ABS ||
|
instructions == LDX_ABS ||
|
| Line 1216... |
Line 1257... |
if (PCL + Y > 255) {
|
if (PCL + Y > 255) {
|
more_cycles = TRUE;
|
more_cycles = TRUE;
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == STA_ABX ||
|
|
instructions == STA_ABY ||
|
|
instructions == JMP_IND
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (addr != PC) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 1 (WRITE)");
|
|
};
|
|
PC = PC + 1;
|
|
};
|
|
(
|
instructions == LDA_ZPG ||
|
instructions == LDA_ZPG ||
|
instructions == LDX_ZPG ||
|
instructions == LDX_ZPG ||
|
instructions == LDY_ZPG ||
|
instructions == LDY_ZPG ||
|
instructions == EOR_ZPG ||
|
instructions == EOR_ZPG ||
|
instructions == AND_ZPG ||
|
instructions == AND_ZPG ||
|
instructions == ORA_ZPG ||
|
instructions == ORA_ZPG ||
|
instructions == ADC_ZPG ||
|
instructions == ADC_ZPG ||
|
instructions == SBC_ZPG ||
|
instructions == SBC_ZPG ||
|
instructions == CMP_ZPG ||
|
instructions == CMP_ZPG ||
|
|
instructions == CPX_ZPG ||
|
|
instructions == CPY_ZPG ||
|
instructions == BIT_ZPG ||
|
instructions == BIT_ZPG ||
|
instructions == ASL_ZPG ||
|
instructions == ASL_ZPG ||
|
instructions == LSR_ZPG ||
|
instructions == LSR_ZPG ||
|
instructions == ROL_ZPG ||
|
instructions == ROL_ZPG ||
|
instructions == ROR_ZPG ||
|
instructions == ROR_ZPG ||
|
| Line 1332... |
Line 1394... |
// dut_error("ADDR should be equal SP!");
|
// dut_error("ADDR should be equal SP!");
|
// };
|
// };
|
// SP = SP - 1;
|
// SP = SP - 1;
|
//};
|
//};
|
(
|
(
|
|
instructions == STA_ABX
|
|
) : {
|
|
if (alu_opcode != instructions) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 1) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (PCL + X > 255) {
|
|
if (addr[7:0] != PCL + X - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + X) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 1 (WRITE)");
|
|
};
|
|
};
|
|
(
|
|
instructions == STA_ABY
|
|
) : {
|
|
if (alu_opcode != instructions) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 1) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (PCL + Y > 255) {
|
|
if (addr[7:0] != PCL + Y - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + Y) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 1 (WRITE)");
|
|
};
|
|
};
|
|
(
|
instructions == LDA_ZPX ||
|
instructions == LDA_ZPX ||
|
instructions == LDY_ZPX ||
|
instructions == LDY_ZPX ||
|
instructions == EOR_ZPX ||
|
instructions == EOR_ZPX ||
|
instructions == AND_ZPX ||
|
instructions == AND_ZPX ||
|
instructions == ORA_ZPX ||
|
instructions == ORA_ZPX ||
|
| Line 1437... |
Line 1551... |
};
|
};
|
};
|
};
|
};
|
};
|
(
|
(
|
instructions == LDA_IDY ||
|
instructions == LDA_IDY ||
|
--instructions == STA_IDY ||
|
instructions == STA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == EOR_IDY ||
|
instructions == EOR_IDY ||
|
instructions == AND_IDY ||
|
instructions == AND_IDY ||
|
instructions == ADC_IDY ||
|
instructions == ADC_IDY ||
|
instructions == CMP_IDY ||
|
instructions == CMP_IDY ||
|
| Line 1462... |
Line 1576... |
if (PCL + Y > 255) {
|
if (PCL + Y > 255) {
|
more_cycles = TRUE;
|
more_cycles = TRUE;
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == JMP_IND
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != pointer) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (addr[12:8] != pointer_h[4:0]) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
(
|
instructions == LDX_ZPY ||
|
instructions == LDX_ZPY ||
|
instructions == LDA_ABY ||
|
instructions == LDA_ABY ||
|
instructions == LDX_ABY ||
|
instructions == LDX_ABY ||
|
instructions == EOR_ABY ||
|
instructions == EOR_ABY ||
|
instructions == AND_ABY ||
|
instructions == AND_ABY ||
|
| Line 1499... |
Line 1632... |
instructions == ADC_ABS ||
|
instructions == ADC_ABS ||
|
instructions == AND_ABS ||
|
instructions == AND_ABS ||
|
instructions == ASL_ABS ||
|
instructions == ASL_ABS ||
|
instructions == BIT_ABS ||
|
instructions == BIT_ABS ||
|
instructions == CMP_ABS ||
|
instructions == CMP_ABS ||
|
|
instructions == CPX_ABS ||
|
|
instructions == CPY_ABS ||
|
instructions == DEC_ABS ||
|
instructions == DEC_ABS ||
|
instructions == EOR_ABS ||
|
instructions == EOR_ABS ||
|
instructions == INC_ABS ||
|
instructions == INC_ABS ||
|
instructions == LDA_ABS ||
|
instructions == LDA_ABS ||
|
instructions == LDX_ABS ||
|
instructions == LDX_ABS ||
|
| Line 1688... |
Line 1823... |
if (addr != SP + 256) {
|
if (addr != SP + 256) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
SP = SP - 1;
|
SP = SP - 1;
|
};
|
};
|
|
(
|
|
instructions == JMP_IND
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (pointer + 1 > 255) {
|
|
if (addr[7:0] != pointer + 1 - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != pointer + 1) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
-- TODO: This is the correct behaviour expected from spec
|
|
--if (addr[12:8] != pointer_h[4:0]) {
|
|
-- print addr[7:0], pointer;
|
|
-- print addr[12:8], pointer_h[4:0];
|
|
-- dut_error("ADDR should be equal SP!");
|
|
--};
|
|
PC[7:0] = PCL;
|
|
PC[12:8] = PCH[4:0];
|
|
};
|
//JSR_ABS : {
|
//JSR_ABS : {
|
// if (alu_opcode.as_a(byte) != 0) {
|
// if (alu_opcode.as_a(byte) != 0) {
|
// dut_error("Opcode is Wrong!");
|
// dut_error("Opcode is Wrong!");
|
// };
|
// };
|
// if (mem_rw != 1) {
|
// if (mem_rw != 1) {
|
| Line 1734... |
Line 1900... |
else {
|
else {
|
if (addr[7:0] != pointer + X + 1) {
|
if (addr[7:0] != pointer + X + 1) {
|
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
|
if (addr[12:8] != 0) {
|
|
print addr[12:8], PCH[4:0];
|
|
dut_error("ADDR is wrong");
|
|
};
|
};
|
};
|
(
|
(
|
instructions == LDA_IDY ||
|
instructions == LDA_IDY ||
|
--instructions == STA_IDY ||
|
instructions == STA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == EOR_IDY ||
|
instructions == EOR_IDY ||
|
instructions == AND_IDY ||
|
instructions == AND_IDY ||
|
instructions == ADC_IDY ||
|
instructions == ADC_IDY ||
|
instructions == CMP_IDY ||
|
instructions == CMP_IDY ||
|
| Line 1764... |
Line 1934... |
else {
|
else {
|
if (addr[7:0] != PCL + Y) {
|
if (addr[7:0] != PCL + Y) {
|
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
|
-- TODO: This is the expected behavior (took from spec)
|
|
-- addr[12:8] is 0 or 1 acording to PCL + Y > 255
|
|
--if (addr[12:8] != PCH[4:0]) {
|
|
-- print addr[12:8], PCH[4:0];
|
|
-- dut_error("ADDR is wrong");
|
|
--};
|
};
|
};
|
(
|
(
|
instructions == STA_IDX
|
instructions == STA_IDX
|
) : {
|
) : {
|
if (alu_opcode != instructions) {
|
if (alu_opcode != instructions) {
|
| Line 1789... |
Line 1965... |
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == STA_ABX
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (PCL + X > 255) {
|
|
if (addr[7:0] != PCL + X - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (addr[12:8] != PCH + 1) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + X) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 1 (WRITE)");
|
|
};
|
|
};
|
|
(
|
|
instructions == STA_ABY
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (PCL + Y > 255) {
|
|
if (addr[7:0] != PCL + Y - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (addr[12:8] != PCH + 1) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + Y) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 1 (WRITE)");
|
|
};
|
|
};
|
|
(
|
instructions == RTI_IMP
|
instructions == RTI_IMP
|
) : {
|
) : {
|
if (alu_opcode != instructions) {
|
if (alu_opcode != instructions) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
| Line 2074... |
Line 2308... |
print PCL + Y, addr[7:0];
|
print PCL + Y, addr[7:0];
|
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == STA_IDY
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (PCL + Y > 255) {
|
|
if (addr[7:0] != PCL + Y - 256) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
if (addr[12:8] != PCH[4:0] + 1) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + Y) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
};
|
|
(
|
instructions == STA_IDX
|
instructions == STA_IDX
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
