| Line 164... |
Line 164... |
instruction == RTI_IMP ||
|
instruction == RTI_IMP ||
|
instruction == RTS_IMP
|
instruction == RTS_IMP
|
) : {
|
) : {
|
new_state = CYCLE_3;
|
new_state = CYCLE_3;
|
};
|
};
|
//JSR_ABS : {
|
instruction == JSR_ABS : {
|
// new_state = CYCLE_3;
|
new_state = CYCLE_3;
|
// PCL = input.data_in;
|
PCL = input.data_in;
|
//};
|
};
|
(
|
(
|
instruction == ADC_ABS ||
|
instruction == ADC_ABS ||
|
instruction == ASL_ABS ||
|
instruction == ASL_ABS ||
|
instruction == BIT_ABS ||
|
instruction == BIT_ABS ||
|
instruction == AND_ABS ||
|
instruction == AND_ABS ||
|
| Line 293... |
Line 293... |
};
|
};
|
};
|
};
|
};
|
};
|
CYCLE_3 : {
|
CYCLE_3 : {
|
case {
|
case {
|
//JSR_ABS : {
|
instruction == JSR_ABS : {
|
// new_state = CYCLE_4;
|
new_state = CYCLE_4;
|
// PCH = input.data_in;
|
// PCH = input.data_in;
|
//};
|
};
|
(
|
(
|
instruction == BRK_IMP ||
|
instruction == BRK_IMP ||
|
instruction == PLA_IMP ||
|
instruction == PLA_IMP ||
|
instruction == PLP_IMP ||
|
instruction == PLP_IMP ||
|
instruction == RTI_IMP ||
|
instruction == RTI_IMP ||
|
| Line 420... |
Line 420... |
};
|
};
|
};
|
};
|
};
|
};
|
CYCLE_4 : {
|
CYCLE_4 : {
|
case {
|
case {
|
//JSR_ABS : {
|
instruction == JSR_ABS : {
|
// new_state = CYCLE_5;
|
new_state = CYCLE_5;
|
//};
|
};
|
(
|
(
|
instruction == RTS_IMP ||
|
instruction == RTS_IMP ||
|
instruction == JMP_IND
|
instruction == JMP_IND
|
) : {
|
) : {
|
new_state = CYCLE_5;
|
new_state = CYCLE_5;
|
| Line 516... |
Line 516... |
};
|
};
|
};
|
};
|
};
|
};
|
CYCLE_5 : {
|
CYCLE_5 : {
|
case {
|
case {
|
//JSR_ABS : {
|
instruction == JSR_ABS : {
|
// new_state = CYCLE_6;
|
new_state = CYCLE_6;
|
//};
|
};
|
(
|
(
|
instruction == RTI_IMP
|
instruction == RTI_IMP
|
) : {
|
) : {
|
new_state = CYCLE_6;
|
new_state = CYCLE_6;
|
PCL = input.data_in;
|
PCL = input.data_in;
|
| Line 600... |
Line 600... |
) : {
|
) : {
|
new_state = CYCLE_7;
|
new_state = CYCLE_7;
|
PCL = input.data_in;
|
PCL = input.data_in;
|
};
|
};
|
(
|
(
|
instructions == RTI_IMP
|
instruction == RTI_IMP
|
|
) : {
|
|
new_state = CYCLE_1;
|
|
PCH = input.data_in;
|
|
};
|
|
(
|
|
instruction == JSR_ABS
|
) : {
|
) : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
PCH = input.data_in;
|
PCH = input.data_in;
|
};
|
};
|
(
|
(
|
| Line 909... |
Line 915... |
instructions == EOR_IDY ||
|
instructions == EOR_IDY ||
|
instructions == AND_IDY ||
|
instructions == AND_IDY ||
|
instructions == ADC_IDY ||
|
instructions == ADC_IDY ||
|
instructions == CMP_IDY ||
|
instructions == CMP_IDY ||
|
instructions == SBC_IDY ||
|
instructions == SBC_IDY ||
|
instructions == JMP_IND
|
instructions == JMP_IND ||
|
|
instructions == JSR_ABS
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 1048... |
Line 1055... |
if (addr != SP + 256) {
|
if (addr != SP + 256) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
SP = SP - 1;
|
SP = SP - 1;
|
};
|
};
|
//JSR_ABS : {
|
instructions == JSR_ABS : {
|
// if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
// dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
// };
|
};
|
// if (mem_rw != 0) {
|
if (mem_rw != 0) {
|
// dut_error("MEM_RW should be 1 (WRITE)");
|
dut_error("MEM_RW should be 1 (WRITE)");
|
// };
|
};
|
// if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
// dut_error("JSR_IMP is Wrong!");
|
dut_error("JSR_IMP is Wrong!");
|
// };
|
};
|
// if (addr != PC) {
|
if (addr != SP + 256) {
|
// dut_error("ADDR should be equal PC!");
|
dut_error("ADDR should be equal PC!");
|
// };
|
};
|
//};
|
};
|
-- TODO: This is probably an error STA should not use ALU on the third cycle
|
-- TODO: This is probably an error STA should not use ALU on the third cycle
|
(
|
(
|
instructions == STA_ZPX ||
|
instructions == STA_ZPX ||
|
instructions == STX_ZPY ||
|
instructions == STX_ZPY ||
|
instructions == STY_ZPX
|
instructions == STY_ZPX
|
| Line 1375... |
Line 1382... |
if (addr != SP + 256) {
|
if (addr != SP + 256) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
SP = SP - 1;
|
SP = SP - 1;
|
};
|
};
|
//JSR_ABS : {
|
instructions == JSR_ABS : {
|
// if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
// dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
// };
|
};
|
// if (mem_rw != 1) {
|
if (mem_rw != 1) {
|
// dut_error("MEM_RW should be 1 (WRITE)");
|
dut_error("MEM_RW should be 1 (WRITE)");
|
// };
|
};
|
// if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
// dut_error("JSR_ABS is Wrong!");
|
dut_error("JSR_ABS is Wrong!");
|
// };
|
};
|
// if (data_out != PC[7:0]) {
|
if (data_out[4:0] != PC[12:8]) {
|
// dut_error("JSR_ABS is Wrong!");
|
dut_error("JSR_ABS is Wrong!");
|
// };
|
};
|
// if (addr != SP + 256) {
|
if (addr != SP + 256) {
|
// dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
// };
|
};
|
// SP = SP - 1;
|
SP = SP - 1;
|
//};
|
};
|
(
|
(
|
instructions == STA_ABX
|
instructions == STA_ABX
|
) : {
|
) : {
|
if (alu_opcode != instructions) {
|
if (alu_opcode != instructions) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
| Line 1854... |
Line 1861... |
-- dut_error("ADDR should be equal SP!");
|
-- dut_error("ADDR should be equal SP!");
|
--};
|
--};
|
PC[7:0] = PCL;
|
PC[7:0] = PCL;
|
PC[12:8] = PCH[4:0];
|
PC[12:8] = PCH[4:0];
|
};
|
};
|
//JSR_ABS : {
|
instructions == JSR_ABS : {
|
// if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
// dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
// };
|
};
|
// if (mem_rw != 1) {
|
if (mem_rw != 1) {
|
// dut_error("MEM_RW should be 1 (WRITE)");
|
dut_error("MEM_RW should be 1 (WRITE)");
|
// };
|
};
|
// if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
// dut_error("JSR_ABS is Wrong!");
|
dut_error("JSR_ABS is Wrong!");
|
// };
|
};
|
// if (data_out != PC[12:8]) {
|
if (data_out != PC[7:0]) {
|
// dut_error("JSR_ABS is Wrong!");
|
dut_error("JSR_ABS is Wrong!");
|
// };
|
};
|
// if (addr != SP + 256) {
|
if (addr != SP + 256) {
|
// dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
// };
|
};
|
// SP = SP - 1;
|
SP = SP - 1;
|
//};
|
};
|
(
|
(
|
instructions == LDA_IDX ||
|
instructions == LDA_IDX ||
|
instructions == ORA_IDX ||
|
instructions == ORA_IDX ||
|
instructions == EOR_IDX ||
|
instructions == EOR_IDX ||
|
instructions == AND_IDX ||
|
instructions == AND_IDX ||
|
| Line 1907... |
Line 1914... |
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
(
|
(
|
instructions == LDA_IDY ||
|
instructions == LDA_IDY ||
|
instructions == STA_IDY ||
|
//instructions == STA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == ORA_IDY ||
|
instructions == EOR_IDY ||
|
instructions == EOR_IDY ||
|
instructions == AND_IDY ||
|
instructions == AND_IDY ||
|
instructions == ADC_IDY ||
|
instructions == ADC_IDY ||
|
instructions == CMP_IDY ||
|
instructions == CMP_IDY ||
|
| Line 1965... |
Line 1972... |
dut_error("ADDR is wrong");
|
dut_error("ADDR is wrong");
|
};
|
};
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == STA_IDY
|
|
) : {
|
|
if (alu_opcode != instructions) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 1) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (pointer + Y > 255) {
|
|
if (addr[7:0] != pointer + Y - 256) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != pointer + Y) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
};
|
|
|
|
(
|
instructions == STA_ABX
|
instructions == STA_ABX
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
| Line 2238... |
Line 2269... |
if (addr != 13'b1111111111110) {
|
if (addr != 13'b1111111111110) {
|
dut_error("BRK_IMP is Wrong!");
|
dut_error("BRK_IMP is Wrong!");
|
};
|
};
|
PC[7:0] = PCL;
|
PC[7:0] = PCL;
|
};
|
};
|
//JSR_ABS : {
|
instructions == JSR_ABS : {
|
// if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
// dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
// };
|
};
|
// if (mem_rw != 0) {
|
if (mem_rw != 0) {
|
// dut_error("MEM_RW should be 1 (WRITE)");
|
dut_error("MEM_RW should be 1 (WRITE)");
|
// };
|
};
|
// if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
// dut_error("JSR_ABS is Wrong!");
|
dut_error("JSR_ABS is Wrong!");
|
// };
|
};
|
// if (addr != PC) {
|
if (addr != PC) {
|
// dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
// };
|
};
|
// PC [7:0] = PCL;
|
PC [7:0] = PCL;
|
// PC[12:8] = PCH[4:0];
|
PC[12:8] = PCH[4:0];
|
//};
|
};
|
(
|
(
|
instructions == LDA_IDX ||
|
instructions == LDA_IDX ||
|
instructions == ORA_IDX ||
|
instructions == ORA_IDX ||
|
instructions == EOR_IDX ||
|
instructions == EOR_IDX ||
|
instructions == AND_IDX ||
|
instructions == AND_IDX ||
|
