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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [controller_test.v] - Diff between revs 222 and 223

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Rev 222	Rev 223
Line 43...	Line 43...
`////////////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////////////`

`include "timescale.v"	`include "timescale.v"

`//module vga_tester (reset_n, clk_50);`	`//module vga_tester (reset_n, clk_50);`
`module vga_tester(line, vert_counter);`	`module controller_test(line, vert_counter);`

`//input reset_n;`	`//input reset_n;`
`//input clk_50;`	`//input clk_50;`

`output reg [479:0] line;`	`output reg [479:0] line;`
Line 84...	Line 84...

`always @ (posedge clk_50 or negedge reset_n) begin`	`always @ (posedge clk_50 or negedge reset_n) begin`
`if (reset_n == 0) begin`	`if (reset_n == 0) begin`
`clk_358 <= 1'b0;`	`clk_358 <= 1'b0;`
`counter <= 4'd0;`	`counter <= 4'd0;`
`vert_counter <= 6'd0;`
`red <= 4'b1010;`	`red <= 4'b1010;`
`green <= 4'b0001;`	`green <= 4'b0001;`
`blue <= 4'b1110;`	`blue <= 4'b1110;`
`line <= 480'd0;`
`end`	`end`
`else begin`	`else begin`
`if (counter == 4'h6) begin`	`if (counter == 4'h6) begin`
`clk_358 <= !clk_358;`	`clk_358 <= !clk_358;`
`counter <= 4'd0;`	`counter <= 4'd0;`
Line 105...	Line 103...



`always @ (posedge clk_358 or negedge reset_n) begin`	`always @ (posedge clk_358 or negedge reset_n) begin`
`if (reset_n == 0) begin`	`if (reset_n == 0) begin`
	`vert_counter <= 6'd0;`
	`line <= 480'd0;`
`end`	`end`
`else begin`	`else begin`

`line <= {pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9,`	`line <= {pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9,`
`pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9,`	`pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9,`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [controller_test.v] - Diff between revs 222 and 223