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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module controller_test(reset_n, clk_50, line, vert_counter);
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module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter);
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input reset_n;
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input reset_n;
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input clk_50;
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input clk_50;
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output reg [479:0] line;
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output reg [11:0] pixel;
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output reg [4:0] vert_counter;
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output reg [8:0] vert_counter;
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output reg [7:0] hor_counter;
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reg clk_358; // 3.58mhz
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reg clk_358; // 3.58mhz
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reg [3:0] counter;
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reg [3:0] counter;
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reg [3:0] red;
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reg [3:0] red;
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reg [3:0] green;
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reg [3:0] green;
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reg [3:0] blue;
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reg [3:0] blue;
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reg [11:0] pixel0;
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reg [11:0] pixel1;
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reg [11:0] pixel2;
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reg [11:0] pixel3;
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reg [11:0] pixel4;
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reg [11:0] pixel5;
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reg [11:0] pixel6;
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reg [11:0] pixel7;
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reg [11:0] pixel8;
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reg [11:0] pixel9;
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always @ (posedge clk_50 or negedge reset_n) begin
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always @ (posedge clk_50 or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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clk_358 <= 1'b0;
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clk_358 <= 1'b0;
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counter <= 4'd0;
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counter <= 4'd0;
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red <= 4'b1010;
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red <= 4'b1010;
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green <= 4'b0001;
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green <= 4'b0001;
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blue <= 4'b1110;
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blue <= 4'b1110;
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end
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end
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else begin
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else begin
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red <= 4'b1010;
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green <= 4'b0001;
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blue <= 4'b1110;
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if (counter == 4'h6) begin
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if (counter == 4'h6) begin
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clk_358 <= !clk_358;
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clk_358 <= !clk_358;
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counter <= 4'd0;
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counter <= 4'd0;
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end
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end
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else begin
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else begin
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always @ (posedge clk_358 or negedge reset_n) begin
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always @ (posedge clk_358 or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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vert_counter <= 6'd0;
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vert_counter <= 6'd0;
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line <= 480'd0;
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hor_counter <= 8'd0;
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$write("NEVER!");
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vert_counter = 9'd0;
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end
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end
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else begin
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else begin
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if (hor_counter == 8'd227) begin // last colum
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hor_counter <= 8'd0;
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line <= {pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9,
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if (vert_counter == 9'd261) begin // last line
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pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9,
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vert_counter <= 9'd0;
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pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9,
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end
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pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9};
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else begin
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vert_counter <= vert_counter + 9'd1;
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if (vert_counter == 5'd29) begin
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end
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vert_counter <= 6'd0;
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end
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end
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else begin
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else begin
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vert_counter <= vert_counter + 5'd1;
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hor_counter <= hor_counter + 8'd1;
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end
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end
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end
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end
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end
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end
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always @(*) begin
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always @(*) begin // comb logic
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pixel0 = {red, green, blue};
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pixel = {red, green, blue};
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pixel1 = {red, green, blue};
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pixel2 = {red, green, blue};
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pixel3 = {red, green, blue};
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pixel4 = {red, green, blue};
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pixel5 = {red, green, blue};
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pixel6 = {red, green, blue};
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pixel7 = {red, green, blue};
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pixel8 = {red, green, blue};
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pixel9 = {red, green, blue};
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end
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end
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endmodule
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endmodule
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