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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [controller_test.v] - Diff between revs 231 and 232
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Rev 232 |
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter);
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module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter, clk_358);
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input reset_n;
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input reset_n;
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input clk_50;
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input clk_50;
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output reg [11:0] pixel;
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output reg [11:0] pixel;
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output reg [8:0] vert_counter;
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output reg [8:0] vert_counter;
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output reg [7:0] hor_counter;
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output reg [7:0] hor_counter;
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reg clk_358; // 3.58mhz
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output reg clk_358; // 3.58mhz
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reg [3:0] counter;
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reg [3:0] counter;
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reg [3:0] red;
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reg [3:0] red;
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reg [3:0] green;
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reg [3:0] green;
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reg [3:0] blue;
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reg [3:0] blue;
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counter <= counter + 4'd1;
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counter <= counter + 4'd1;
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end
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end
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end
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end
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end
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end
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always @ (posedge clk_358 or negedge reset_n) begin
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always @ (posedge clk_358 or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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hor_counter <= 8'd0;
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hor_counter <= 8'd0;
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vert_counter <= 9'd0;
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vert_counter <= 9'd0;
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end
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end
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end
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end
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end
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end
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end
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end
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always @(*) begin // comb logic
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always @(*) begin // comb logic
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if (hor_counter < 10) begin
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pixel = {red, green, blue};
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pixel = {red, green, blue};
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end
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end
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else begin
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pixel = {red, red, green};
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end
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end
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endmodule
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endmodule
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