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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t2600_kb_tb.v] - Diff between revs 211 and 214
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Rev 214 |
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Line 45... |
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module t2600_kb_tb();
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module t2600_kb_tb();
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// all inputs are regs
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// all inputs are regs
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reg clk;
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reg clk;
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reg reset_n;
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reg reset_n;
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reg kd;
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reg kc;
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// all outputs are wires
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// all outputs are wires
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wire [15:0] io_lines;
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wire [15:0] io_lines;
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initial clk = 0;
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always #10 clk <= ~clk;
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always #10 clk <= ~clk;
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always @(posedge clk) begin
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initial begin
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//$display("reset is %b", reset_n);
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clk = 1'b0;
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//$display("alu_enable is %b", alu_enable);
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reset_n = 1'b1;
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//$display("alu_opcode is %h", alu_opcode);
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kd = 1'b0;
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//$display("alu_a is %d", alu_a);
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kc = 1'b0;
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#10;
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reset_n = 1'b0;
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#40000;
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$finish;
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end
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always @(clk) begin
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kc = $random;
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kd = $random;
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end
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end
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t2600_kb t2600_kb (
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T2600_KB T2600_KB (
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.CLK (clk),
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.CLK (clk),
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.RST (reset_n),
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.RST (reset_n),
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.io_lines (alu_enable)
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.io_lines (io_lines),
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.KC (kc),
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.KD (kd)
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);
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);
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endmodule
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endmodule
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