| Line 42... |
Line 42... |
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
|
|
`include "timescale.v"
|
`include "timescale.v"
|
|
|
`include "T6507LP_ALU.v"
|
//`include "T6507LP_ALU.v"
|
`include "t6507lp_fsm.v"
|
//`include "t6507lp_fsm.v"
|
|
|
module t6507lp(clk, reset_n, data_in, rw_mem, data_out, address);
|
module t6507lp(clk, reset_n, data_in, rw_mem, data_out, address);
|
parameter [3:0] DATA_SIZE = 4'd8;
|
parameter [3:0] DATA_SIZE = 4'd8;
|
parameter [3:0] ADDR_SIZE = 4'd13;
|
parameter [3:0] ADDR_SIZE = 4'd13;
|
|
|
| Line 69... |
Line 69... |
wire [DATA_SIZE_:0] alu_opcode;
|
wire [DATA_SIZE_:0] alu_opcode;
|
wire [DATA_SIZE_:0] alu_a;
|
wire [DATA_SIZE_:0] alu_a;
|
wire alu_enable;
|
wire alu_enable;
|
|
|
// `include "T6507LP_Package.v"
|
// `include "T6507LP_Package.v"
|
|
//TODO change rw_mem to mem_rw
|
t6507lp_fsm #(DATA_SIZE, ADDR_SIZE) t6507lp_fsm(
|
t6507lp_fsm #(DATA_SIZE, ADDR_SIZE) t6507lp_fsm(
|
.clk (clk),
|
.clk (clk),
|
.reset_n (reset_n),
|
.reset_n (reset_n),
|
.alu_result (alu_result),
|
.alu_result (alu_result),
|
.alu_status (alu_status),
|
.alu_status (alu_status),
|
.data_in (data_in),
|
.data_in (data_in),
|
.alu_x (alu_x),
|
.alu_x (alu_x),
|
.alu_y (alu_y),
|
.alu_y (alu_y),
|
.address (address),
|
.address (address),
|
.mem_rw (mem_rw),
|
.mem_rw (rw_mem),
|
.data_out (data_out),
|
.data_out (data_out),
|
.alu_opcode (alu_opcode),
|
.alu_opcode (alu_opcode),
|
.alu_a (alu_a),
|
.alu_a (alu_a),
|
.alu_enable (alu_enable)
|
.alu_enable (alu_enable)
|
);
|
);
|
