| Line 70... |
Line 70... |
`include "t6507lp_package.v"
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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begin
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begin
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if (reset_n == 0) begin
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if (reset_n == 0) begin
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//$display("RESTART");
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$display("RESTART");
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alu_result <= 0;
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alu_result <= 0;
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alu_status[C] <= 0;
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alu_status[C] <= 0;
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alu_status[N] <= 0;
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alu_status[N] <= 0;
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alu_status[V] <= 0;
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alu_status[V] <= 0;
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alu_status[5] <= 1;
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alu_status[Z] <= 1;
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alu_status[Z] <= 1;
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alu_status[I] <= 0;
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alu_status[I] <= 0;
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alu_status[B] <= 0;
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alu_status[B] <= 0;
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alu_status[D] <= 0;
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alu_status[D] <= 0;
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A <= 0;
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A <= 0;
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| Line 86... |
Line 87... |
Y <= 0;
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Y <= 0;
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alu_x <= 0;
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alu_x <= 0;
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alu_y <= 0;
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alu_y <= 0;
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end
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end
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else if ( alu_enable == 1 ) begin
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else if ( alu_enable == 1 ) begin
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//$display("A = %h result = %h", A, result);
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//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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case (alu_opcode)
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case (alu_opcode)
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
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ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
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EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
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ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
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ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
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SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
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SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
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LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
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LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
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begin
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begin
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$display("A = %h result = %h", A, result);
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//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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A <= result;
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A <= result;
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alu_result <= result;
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alu_result <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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| Line 116... |
Line 122... |
begin
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begin
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Y <= result;
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Y <= result;
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alu_y <= result;
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alu_y <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX,
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
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ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS,
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CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS, PHP_IMP :
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CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,
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CPY_ZPG, CPY_ABS, PHP_IMP :
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begin
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begin
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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SEC_IMP :
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SEC_IMP :
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begin
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begin
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| Line 165... |
Line 169... |
begin
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begin
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alu_status[Z] <= STATUS[Z];
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alu_status[Z] <= STATUS[Z];
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alu_status[V] <= alu_a[6];
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alu_status[V] <= alu_a[6];
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alu_status[N] <= alu_a[7];
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alu_status[N] <= alu_a[7];
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end
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end
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INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX :
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INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
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ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
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ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
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begin
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begin
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alu_result <= result;
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alu_result <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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default : begin
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default : begin
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| Line 183... |
Line 189... |
bcd1 = A;
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bcd1 = A;
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bcd2 = alu_a;
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bcd2 = alu_a;
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result = alu_result;
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result = alu_result;
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STATUS[C] = alu_status[C];
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STATUS[C] = alu_status[C];
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STATUS[V] = alu_status[V];
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STATUS[V] = alu_status[V];
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STATUS[5] = 1;
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STATUS[B] = alu_status[B];
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STATUS[B] = alu_status[B];
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STATUS[I] = alu_status[I];
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STATUS[I] = alu_status[I];
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STATUS[D] = alu_status[D];
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STATUS[D] = alu_status[D];
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case (alu_opcode)
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case (alu_opcode)
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| Line 312... |
Line 317... |
end
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end
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if (bcd2[7:4] > 9) begin
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if (bcd2[7:4] > 9) begin
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bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
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bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
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end
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end
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end
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end
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$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
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$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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{STATUS[C],result} = bcd1 + bcd2 + alu_status[C];
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{STATUS[C],result} = bcd1 + bcd2 + alu_status[C];
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if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
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if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
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STATUS[V] = 1;
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STATUS[V] = 1;
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else
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else
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STATUS[V] = 0;
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STATUS[V] = 0;
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| Line 328... |
Line 334... |
if (result[7:4] > 9) begin
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if (result[7:4] > 9) begin
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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STATUS[C] = 1;
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STATUS[C] = 1;
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end
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end
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end
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end
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$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
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$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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end
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end
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// AND - Logical AND
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// AND - Logical AND
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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result = A & alu_a;
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result = A & alu_a;
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