| Line 70... |
Line 70... |
`include "t6507lp_package.v"
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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begin
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begin
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if (reset_n == 0) begin
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if (reset_n == 0) begin
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$display("RESTART");
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//$display("RESTART");
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alu_result <= 0;
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alu_result <= 0;
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alu_status[C] <= 0;
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alu_status[C] <= 0;
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alu_status[N] <= 0;
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alu_status[N] <= 0;
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alu_status[V] <= 0;
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alu_status[V] <= 0;
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alu_status[5] <= 1;
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alu_status[5] <= 1;
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| Line 161... |
Line 161... |
begin
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begin
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alu_status[B] <= 0;
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alu_status[B] <= 0;
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end
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end
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PLP_IMP, RTI_IMP :
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PLP_IMP, RTI_IMP :
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begin
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begin
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alu_status <= alu_a;
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alu_status[C] <= alu_a[C];
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alu_status[Z] <= alu_a[Z];
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alu_status[I] <= alu_a[I];
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alu_status[D] <= alu_a[D];
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alu_status[B] <= alu_a[B];
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alu_status[V] <= alu_a[V];
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alu_status[N] <= alu_a[N];
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end
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end
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BIT_ZPG, BIT_ABS :
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BIT_ZPG, BIT_ABS :
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begin
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begin
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alu_status[Z] <= STATUS[Z];
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alu_status[Z] <= STATUS[Z];
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alu_status[V] <= alu_a[6];
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alu_status[V] <= alu_a[6];
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Line 192... |
end
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end
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always @ (*) begin
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always @ (*) begin
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bcd1 = A;
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bcd1 = A;
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bcd2 = alu_a;
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bcd2 = alu_a;
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//result = alu_result;
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result = alu_result;
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//STATUS[C] = STATUS[C];
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STATUS[N] = alu_status[N];
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//STATUS[V] = STATUS[V];
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STATUS[C] = alu_status[C];
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//STATUS[B] = STATUS[B];
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STATUS[V] = alu_status[V];
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//STATUS[I] = STATUS[I];
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STATUS[B] = alu_status[B];
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//STATUS[D] = STATUS[D];
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STATUS[I] = alu_status[I];
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STATUS[D] = alu_status[D];
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STATUS[Z] = alu_status[Z];
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STATUS[N] = alu_status[N];
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STATUS[5] = alu_status[5];
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case (alu_opcode)
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case (alu_opcode)
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// BIT - Bit Test
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// BIT - Bit Test
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BIT_ZPG, BIT_ABS: begin
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BIT_ZPG, BIT_ABS: begin
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result = A & alu_a;
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result = A & alu_a;
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Line 344... |
if (result[7:4] > 9) begin
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if (result[7:4] > 9) begin
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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result = result[7:4] + 6; // A = A - 10 and A = A + 16
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STATUS[C] = 1;
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STATUS[C] = 1;
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end
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end
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end
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end
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$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
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//$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
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$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
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end
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end
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// AND - Logical AND
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// AND - Logical AND
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
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result = A & alu_a;
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result = A & alu_a;
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